# -*- coding: utf-8 -*- # Copyright (c) 2015 Jason Power # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer; # redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution; # neither the name of the copyright holders nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Jason Lowe-Power """ This file creates a system with Ruby caches and runs the ruby random tester See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book also needs to be updated. For now, email Jason """ from __future__ import print_function from __future__ import absolute_import # import the m5 (gem5) library created when gem5 is built import m5 # import all of the SimObjects from m5.objects import * from test_caches import TestCacheSystem # create the system we are going to simulate system = System() # Set the clock fequency of the system (and all of its children) system.clk_domain = SrcClockDomain() system.clk_domain.clock = '1GHz' system.clk_domain.voltage_domain = VoltageDomain() # Set up the system system.mem_mode = 'timing' # Use timing accesses system.mem_ranges = [AddrRange('512MB')] # Create an address range # Create the tester system.tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10, num_cpus = 2) # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] # Create the Ruby System system.caches = TestCacheSystem() system.caches.setup(system, system.tester, [system.mem_ctrl]) # set up the root SimObject and start the simulation root = Root(full_system = False, system = system) # Not much point in this being higher than the L1 latency m5.ticks.setGlobalFrequency('1ns') # instantiate all of the objects we've created above m5.instantiate() print("Beginning simulation!") exit_event = m5.simulate() print('Exiting @ tick {} because {}'.format( m5.curTick(), exit_event.getCause()) )