Lines Matching defs:system
55 # Create a system with a Crossbar and a TrafficGenerator as CPU:
56 system = System()
57 system.membus = IOXBar(width = 16)
58 system.physmem = SimpleMemory() # This must be instanciated, even if not needed
59 system.cpu = TrafficGen(config_file = "conf/tgen.cfg")
60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
64 system.tlm = ExternalSlave()
65 system.tlm.addr_ranges = [AddrRange('512MB')]
66 system.tlm.port_type = "tlm_slave"
67 system.tlm.port_data = "transactor"
70 system.cpu.port = system.membus.slave
71 system.system_port = system.membus.slave
72 system.membus.master = system.tlm.port
75 root = Root(full_system = False, system = system)
76 root.system.mem_mode = 'timing'