Lines Matching defs:system
54 # Create a system with a Crossbar and a simple Memory:
55 system = System()
56 system.membus = IOXBar(width = 16)
57 system.physmem = SimpleMemory(range = AddrRange('512MB'))
58 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
62 system.tlm = ExternalMaster()
63 system.tlm.port_type = "tlm_master"
64 system.tlm.port_data = "transactor"
67 system.system_port = system.membus.slave
68 system.physmem.port = system.membus.master
69 system.tlm.port = system.membus.slave
70 system.mem_mode = 'timing'
73 root = Root(full_system = False, system = system)