src/riscv/rv64i.h

195 store(const M& rs2)
201         asm volatile("sb %1,%0" : "=m" (mem) : "r" (rs2));
204         asm volatile("sh %1,%0" : "=m" (mem) : "r" (rs2));
207         asm volatile("sw %1,%0" : "=m" (mem) : "r" (rs2));
210         asm volatile("sd %1,%0" : "=m" (mem) : "r" (rs2));
289 add(int64_t rs1, int64_t rs2)
292     ROP("add", rd, rs1, rs2);
297 sub(int64_t rs1, int64_t rs2)
300     ROP("sub", rd, rs1, rs2);
305 sll(int64_t rs1, int64_t rs2)
308     ROP("sll", rd, rs1, rs2);
313 slt(int64_t rs1, int64_t rs2)
316     ROP("slt", rd, rs1, rs2);
321 sltu(uint64_t rs1, uint64_t rs2)
324     ROP("sltu", rd, rs1, rs2);
329 xor_inst(uint64_t rs1, uint64_t rs2)
332     ROP("xor", rd, rs1, rs2);
337 srl(uint64_t rs1, uint64_t rs2)
340     ROP("srl", rd, rs1, rs2);
345 sra(int64_t rs1, int64_t rs2)
348     ROP("sra", rd, rs1, rs2);
353 or_inst(uint64_t rs1, uint64_t rs2)
356     ROP("or", rd, rs1, rs2);
361 and_inst(uint64_t rs1, uint64_t rs2)
364     ROP("and", rd, rs1, rs2);
401 addw(int64_t rs1,  int64_t rs2)
404     ROP("addw", rd, rs1, rs2);
409 subw(int64_t rs1,  int64_t rs2)
412     ROP("subw", rd, rs1, rs2);
417 sllw(int64_t rs1,  int64_t rs2)
420     ROP("sllw", rd, rs1, rs2);
425 srlw(uint64_t rs1,  uint64_t rs2)
428     ROP("srlw", rd, rs1, rs2);
433 sraw(int64_t rs1,  int64_t rs2)
436     ROP("sraw", rd, rs1, rs2);