isa/rv64ui/srlw.S

4 # srlw.S
7 # Test srlw instruction.
20   TEST_RR_OP( 2,  srlw, 0xffffffff80000000, 0xffffffff80000000, 0  );
21   TEST_RR_OP( 3,  srlw, 0x0000000040000000, 0xffffffff80000000, 1  );
22   TEST_RR_OP( 4,  srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
23   TEST_RR_OP( 5,  srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
24   TEST_RR_OP( 6,  srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
26   TEST_RR_OP( 7,  srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
27   TEST_RR_OP( 8,  srlw, 0x000000007fffffff, 0xffffffffffffffff, 1  );
28   TEST_RR_OP( 9,  srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7  );
29   TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
30   TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
32   TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0  );
33   TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1  );
34   TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7  );
35   TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
36   TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
40   TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
41   TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
42   TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
43   TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
44   TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
50   TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
51   TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
52   TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
58   TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
59   TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
60   TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
62   TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
63   TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
64   TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
65   TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
66   TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
67   TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
69   TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
70   TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
71   TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
72   TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
73   TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
74   TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
76   TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
77   TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
78   TEST_RR_ZEROSRC12( 42, srlw, 0 );
79   TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );