Lines Matching refs:slliw

4 # slliw.S
7 # Test slliw instruction.
20 TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 );
21 TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 );
22 TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
23 TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
24 TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
26 TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
27 TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
28 TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
29 TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
30 TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
32 TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 );
33 TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 );
34 TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 );
35 TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
36 TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
42 TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
48 TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
49 TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
50 TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
52 TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
53 TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
54 TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
56 TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
57 TEST_IMM_ZERODEST( 25, slliw, 31, 28 );