Lines Matching defs:system
38 # system simulated
39 system = System(cpu = cpus,
43 system.voltage_domain = VoltageDomain()
44 system.clk_domain = SrcClockDomain(clock = '1GHz',
45 voltage_domain = system.voltage_domain)
49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
50 voltage_domain = system.voltage_domain)
52 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
53 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
54 system.l2c.cpu_side = system.toL2Bus.master
57 system.l2c.mem_side = system.membus.slave
62 cpu.clk_domain = system.cpu_clk_domain
65 cpu.l1c.mem_side = system.toL2Bus.slave
67 system.system_port = system.membus.slave
70 system.physmem.port = system.membus.master
77 root = Root( full_system = False, system = system )
78 root.system.mem_mode = 'timing'