alpha/palcode/platform.S

183     stq_p _rsum, 0(_raddr);       /* write the right tlintrsum reg */      \
317     stq_p r14, 0(r16)		// Tsunami MISC Register
319     stq_p r14, 0x40(r13)	// Write to TLIPINTR reg
405 //	r0 = 2	stq_p
451         // stq_p
454         stq_p	r18, 0(r17)		// store the data
486         stq_p	r12, 0(r16)		// store out PTE
502         stq_p	r12, 0(r16)		// store out PTE
587         stq_p   r14, 0(r12)                     // clear the ipi interrupt
606         stq_p   r14, 0(r12)                     // clear the rtc interrupt
974         stq_p	r14, 0(r13)			// clear GBUS$SERNUM<6>
1107         stq_p	r9, mchk_crd_mchk_code(r14)
1116         stq_p	r1, mchk_crd_flag(r14)	  	// store flag/frame size
1121         stq_p	r0, mchk_crd_ei_addr(r14)
1122         stq_p	r10, mchk_crd_fill_syn(r14)
1123         stq_p	r8, mchk_crd_ei_stat(r14)
1124         stq_p	r25, mchk_crd_isr(r14)
1224         stq_p 	r8,  0(r0) 		// Store it back if it is still there.
1243         stq_p 	r8,  0(r0) 		// Store it back if it is still there.
1527         stq_p	r31, 0(r13)		// Clear lock_flag
1673         stq_p	r6, 0(r5)			// clear GBUS$SERNUM<6>
1861         stq_p	r4, mchk_flag(r14)			// store flag/frame size
1865         stq_p	r4, mchk_offsets(r14)			// store sys offset/cpu offset into logout frame
1874         stq_p	r6, mchk_mchk_code(r14)
1876         stq_p	r1, mchk_ic_perr_stat(r14)
1878         stq_p	r8, mchk_dc_perr_stat(r14)
1880         stq_p	r9, mchk_sc_addr(r14)
1881         stq_p	r10, mchk_sc_stat(r14)
1882         stq_p	r12, mchk_ei_addr(r14)
1883         stq_p	r13, mchk_bc_tag_addr(r14)
1884         stq_p	r0,  mchk_fill_syn(r14)
1894         stq_p	r25, mchk_ei_stat(r14)
1906         stq_p	r13, mchk_ld_lock(r14)		// and stash it in the frame
2017         stq_p	r25, mchk_exc_addr(r14)
2125         stq_p	r12, mchk_exc_addr(r14)		// exc_addr has not yet been written