Lines Matching refs:r1
1047 mtpr r1, pt1 // save r0 for scratch
1084 srl r13, mces_v_sce, r1 // Get SCE
1086 or r1, r14, r1 // SCE OR PCE, since they share
1092 blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
1096 lda r1, 3(r31) // Set retry and 2nd error flags
1097 sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
1098 stl_p r1, mchk_crd_flag+4(r14) // store flag longword
1113 lda r1, 1(r31) // Set retry flag
1114 sll r1, 63, r9 // Move retry flag to bit 63
1115 lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
1116 stq_p r1, mchk_crd_flag(r14) // store flag/frame size
1129 lda r1, 0xffc4(r31) // Get GBUS$MISCR address
1130 sll r1, 24, r1
1131 ldq_p r1, 0(r1) // Read GBUS$MISCR
1132 sll r1, 16, r1 // shift up to proper field
1135 or r1, r10, r1 // merge MISCR and WHAMI
1136 stl_p r1, mchk_crd_whami(r14) // write to crd logout area
1150 mfpr r1, pt1 // restore r1
1264 // pt1 - saved r1
1301 mtpr r1, pt1 // Stash for scratch
1360 // r1 = pal_base +8
1384 lda r1, -8(r1) // point to start of code
1385 mtpr r1, pal_base // initialize PAL_BASE
1394 ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
1398 or r0, r1, r1 // Set the bit
1400 mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
1404 lda r1,BIT(mcsr_v_sp1)(zero)
1406 mtpr r1, mcsr // MCSR - Super page enabled
1407 lda r1, BIT(dc_mode_v_dc_ena)(r31)
1409 // mtpr r1, dc_mode // turn Dcache on
1420 lda r1, 0x1F(r31)
1421 mtpr r1, ipl // set internal <ipl>=1F
1438 ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
1439 lda r1, 0x1615(r1)
1441 sll r1, 32, r1
1442 ldah r1, 0x1402(r1) // Create lower lw of int_mask
1444 lda r1, 0x0100(r1)
1445 mtpr r1, pt_intmask // Stash in PALtemp
1461 srl r0, pt_misc_v_switch, r1
1462 blbs r1, sys_reset_switch // see if we got here from swppal
1469 lda r1, 0x67(r31)
1470 sll r1, hwint_clr_v_pc0c, r1
1471 mtpr r1, hwint_clr // Clear hardware interrupt requests
1473 lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
1476 or r0, r1, r1 // combine whami and mces
1477 mtpr r1, pt_misc // store whami and mces, swap bit clear
1492 or r31, 1, r1 // get bogus scbb value
1493 mtpr r1, pt_scbb // load scbb
1498 // in r1 with an uncooperative assembler --ali
1499 br r1, kludge_getpcb_addr
1502 ldq_p r19, 0(r1)
1506 addq r19, r1, r1
1507 addq r1,4,r1
1509 // or zero,kludge_initial_pcbb,r1
1510 GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
1512 mtpr r1, pt_pcbb // load pcbb
1513 lda r1, 2(r31) // get a two
1514 sll r1, 32, r1 // gen up upper bits
1515 mtpr r1, mvptbr
1516 mtpr r1, ivptbr
1544 rpcc r1 // get cyccounter
1578 subl r23, r1, r1 // gen new cc offset
1579 insll r1, 4, r1 // << 32
1580 mtpr r1, cc // set new offset
1645 mtpr r1, pt1 // Stash for scratch - 30 instructions
1683 // pt1 - saved r1
1691 // r0, r1, r4, r5, r6, r12, r13, r25 - available
1700 mfpr r1, icperr_stat
1740 and r1, r4, r4 // Timeout reset
1800 and r1, r4, r4
1832 // r1 - icperr_stat
1844 // pt1 - saved r1
1876 stq_p r1, mchk_ic_perr_stat(r14)
1879 mfpr r1, pt1
1946 GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
1947 or r0, r1, r0 // merge mask values
1994 mfpr r1, pt_misc // fetch current pt_misc
1997 bic r1, r4, r1 // clear out old vector field
1998 or r1, r8, r1 // merge in new vector
1999 mtpr r1, pt_misc // save new vector field
2005 mfpr r1, pt1
2161 mtpr r1, pt1 // get a scratch reg
2162 and r11, osfps_m_mode, r1 // get mode bit
2165 beq r1, 1f // if zero we are in kern now
2177 mfpr r1, pt_entArith
2195 mtpr r1, pt10 // Set new PC
2196 mfpr r1, pt1
2236 mtpr r1, pt4
2238 subq r31, 1, r1
2239 sll r1, 42, r1
2240 ldah r1, 1(r1)
2243 mtpr r1, exc_addr
2244 mfpr r1, pt4
2272 GET_IMPURE(r1)
2279 ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3
2280 ldq_p r1, (cns_gpr+8)(r1) // restore r1