Lines Matching refs:r17
222 stq r17, osfsf_a1(sp) // a1
223 or r31, mmcsr_c_acv, r17 // pass mm_csr as a1
289 stq r17, osfsf_a1(sp) // a1
533 stq r17, osfsf_a1(sp) // a1
534 and r25, mm_stat_m_opcode, r17// Clean opocde for a1
676 stq r17, osfsf_a1(sp) // a1
736 stq r17, osfsf_a1(sp)
737 mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
807 stq r17, osfsf_a1(sp) // a1
861 stq r17, osfsf_a1(sp) // a1
862 srl r13, 1, r17 // shift fault bits to right position
871 cmovlbs r17, 1, r17 // a2. acv overrides fox.
1098 mtpr r17, ev5__itb_is // Flush ITB
1103 mtpr r17, ev5__dtb_is // Flush DTB.
1112 mtpr r17, ev5__dtb_is // Flush DTB
1116 mtpr r17, ev5__itb_is // Flush ITB
1302 stq r17, osfsf_a1(sp) // a1
1306 lda r17, mmcsr_c_acv(r31) // assume ACV
1309 cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE
1361 stq r17, osfsf_a1(sp) // a1
1365 and r25, 1, r17 // Isolate kre
1368 xor r17, 1, r17 // map to acv/tnv as a1
1447 stq r17, osfsf_a1(sp) // a1
1448 or r31, mmcsr_c_acv, r17 // assume acv
1466 cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv
1654 stq r17, osfsf_a1(sp) // a1
1799 SAVE_GPR(r17,CNS_Q_GPR+0x88,r1)
2274 RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1)
2658 and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17
2663 or r1, r17, r1 // Update DPC and DSC
2933 // r17/a1 = Va for TBISx instructions
2963 // r17/a1 = Entry Number 0..5
2970 cmpult r17, 6, r22 // see if in range
2977 sll r17, 4, r17 // *16
2979 addq r17, r23, r23 // Get address in table
3078 // option argument in r17
3083 // r17 = 0 disable no counters
3084 // r17 = bitmask disable counters specified in bit mask (1=disable)
3087 // r17 = 0 enable no counters
3088 // r17 = bitmask enable counters specified in bit mask (1=enable)
3091 // r17 = Mux selection (cpu specific)
3096 // r17 = (cpu specific)
3102 // r17 = (cpu specific) indicates interrupt frequencies desired for each
3104 // frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below
3107 // r17 = na
3113 // r17 = value (same format as ev5 pmctr; all counters written simultaneously)
3116 // r17 = 0 enable no counters
3117 // r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear)
3265 // 32(sp) -> r17 (a1)
3283 ldq r17, -2*8(r25) // a1
3341 stq r17, osfsf_a1(sp) // a1
3382 stq r17, osfsf_a1(sp) // a1
3678 stq r17, osfsf_a1(sp) // a1
3787 and r17, r8, r25 // isolate pmctr mux select bits
3805 and r17, r8, r25 // isolate bc_ctl mux select bits
3825 blbc r17, perfmon_dis_ctr1 // do not disable ctr0
3830 srl r17, 1, r17
3831 blbc r17, perfmon_dis_ctr2 // do not disable ctr1
3836 srl r17, 1, r17
3837 blbc r17, perfmon_dis_update // do not disable ctr2
3850 lda r17, 0x3F(r31) // build mask
3851 sll r17, pmctr_v_ctl2, r17 // shift mask to correct position
3852 and r14, r17, r14 // isolate ctl bits
3853 bic r8, r17, r8 // clear out old ctl bits
3899 blbc r17, perfmon_en_ctr1 // do not enable ctr0
3916 srl r17, 1, r17 // get ctr1 enable
3917 blbc r17, perfmon_en_ctr2 // do not enable ctr1
3934 srl r17, 1, r17 // get ctr2 enable
3935 blbc r17, perfmon_en_return // do not enable ctr2 - return
3984 and r17, r8, r25 // isolate pmctr mode bits
3992 lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
3994 cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
4003 blbs r17, perfmon_sp // branch if select processes
4023 and r8, r17, r17
4026 or r17, r14, r14 // or in new frequency select info
4048 and r17, r8, r25 // clear all but ctr fields
4072 and r17, 63, r9
4082 addq r17, 64, r17
4089 ldq_u r8, 0(r17)
4090 xor r17, r16, r9
4097 mskqh r8, r17, r8
4098 mskql r9, r17, r9
4107 ldq_u r8, 8(r17)
4110 lda r17,8(r17)
4124 addq r17, r18, r25
4131 ldq_u r9, 7(r17)
4132 extql r8, r17, r8
4133 extqh r9, r17, r9
4141 addq r17, r10, r17
4143 ldq_u r8, 0(r17)
4150 ldq_u r9, 7(r17)
4151 lda r17, 8(r17)
4152 extql r8, r17, r12
4153 extqh r9, r17, r13
4159 ldq_u r8, 7(r17)
4160 lda r17, 8(r17)
4161 extql r9, r17, r12
4162 extqh r8, r17, r13
4172 extql r9, r17, r9
4173 extqh r8, r17, r8
4180 extql r8, r17, r8
4181 extqh r9, r17, r9