Lines Matching refs:r16
219 stq r16, osfsf_a0(sp) // save regs
220 bic r14, 3, r16 // pass pc/va as a0
231 stq r16, osfsf_pc(sp) // save pc
285 stq r16, osfsf_a0(sp) // a0
536 stq r16, osfsf_a0(sp) // save regs
537 mfpr r16, pt0 // a0 <- va/unlock
669 stq r16, osfsf_a0(sp) // save regs
670 bis r31, osf_a0_opdec, r16 // set a0
742 stq r16, osfsf_a0(sp) // save regs
743 srl r13, exc_sum_v_swc, r16 // shift data to correct position
798 stq r16, osfsf_a0(sp) // save regs
810 bis r31, osf_a0_fen, r16 // set a0
824 bis r31, osf_a0_opdec, r16 // set a0
858 stq r16, osfsf_a0(sp) // save regs
859 bis r25, r31, r16 // a0 <- va
1007 // r16 has new value
1014 mtpr r16, pt_entint
1022 mtpr r16, pt_entarith
1030 mtpr r16, pt_entmm
1038 mtpr r16, pt_entif
1046 mtpr r16, pt_entuna
1054 mtpr r16, pt_entsys
1188 ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr
1211 ldq_p r25, osfpcb_q_usp(r16) // get new usp
1218 ldq_p r30, osfpcb_q_ksp(r16) // get new ksp
1299 stq r16, osfsf_a0(sp) // a0
1300 or r14, r31, r16 // pass pc/va as a0
1308 stq r16, osfsf_pc(sp) // save pc
1358 stq r16, osfsf_a0(sp) // a0
1359 or r14, r31, r16 // pass pc/va as a0
1367 stq r16, osfsf_pc(sp) // save pc
1444 stq r16, osfsf_a0(sp) // a0
1445 or r25, r31, r16 // pass va as a0
1647 stq r16, osfsf_a0(sp) // save regs
1648 bis r31, osf_a0_opdec, r16 // set a0
1798 SAVE_GPR(r16,CNS_Q_GPR+0x80,r1)
2273 RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1)
2520 // arguments in r16....
2550 cmpule r16, 255, r0 // see if a kibble was passed
2551 cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59)
2553 or r16, r31, r3 // set r3 incase this is a address
2556 cmpeq r16, 2, r0 // is it our friend OSF?
2595 // r16 = processor number to interrupt
2654 and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE
2658 and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17
2784 // Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16)
2796 and r16, 1, r16 // clean new fen
2798 sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position
2805 stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB.
2826 // vptptr <- a0 (r16)
2831 mtpr r16, ev5__mvptbr // Load Mbox copy
2832 mtpr r16, ev5__ivptbr // Load Ibox copy
2867 ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme
2868 ldq_p r23, osfpcb_l_cc(r16) // get new asn
2875 mtpr r16, pt_pcbb // set new pcbb
2896 // sysvalue <- a0 (r16)
2902 mtpr r16, pt_sysval // Pad paltemp write
2932 // r16/a0 = TBI type
2938 addq r16, 2, r16 // change range to 0-2
2941 CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range
2943 sll r16, 4, r16 // * 16
2946 addq r23, r16, r23 // addr of our code
2962 // r16/a0 = Address of entry routine
2973 CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc
2994 // PS<IPL> <- a0<2:0> (r16)
3001 and r16, osfps_m_ipl, r16 // clean New ipl
3004 extbl r22, r16, r22 // get mask for this ipl
3007 bis r16, r31, r11 // set new ps
3038 // kgp <- a0 (r16)
3044 mtpr r16, pt_kgp
3056 // usp <- a0 (r16)
3062 mtpr r16, pt_usp
3077 // option selector in r16
3082 // r16 = 0 Disable performance monitoring for one or more cpu's
3086 // r16 = 1 Enable performance monitoring for one or more cpu's
3090 // r16 = 2 Mux select for one or more cpu's
3095 // r16 = 3 Options
3101 // r16 = 4 Interrupt frequency select
3106 // r16 = 5 Read Counters
3112 // r16 = 6 Write Counters
3115 // r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0
3146 cmpeq r16, 1, r0 // check for enable
3149 cmpeq r16, 2, r0 // check for mux ctl
3152 cmpeq r16, 3, r0 // check for options
3155 cmpeq r16, 4, r0 // check for interrupt frequency select
3158 cmpeq r16, 5, r0 // check for counter read request
3161 cmpeq r16, 6, r0 // check for counter write request
3164 cmpeq r16, 7, r0 // check for counter clear/enable request
3167 beq r16, perfmon_dis // br if requested to disable (r16=0)
3264 // 24(sp) -> r16 (a0)
3285 ldq r16, -3*8(r25) // a0
3338 stq r16, osfsf_a0(sp) // save regs
3339 bis r31, osf_a0_bpt, r16 // set a0
3379 stq r16, osfsf_a0(sp) // save regs
3380 bis r31, osf_a0_bugchk, r16 // set a0
3584 // unique <- a0 (r16)
3592 stq_p r16, osfpcb_q_unique(r12)// get new value
3675 stq r16, osfsf_a0(sp) // save regs
3676 bis r31, osf_a0_gentrap, r16// set a0
3796 //orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword
3798 mfpr r16, pt_impure
3799 lda r16, CNS_Q_IPR(r16)
3800 RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
3806 bic r16, r8, r16 // isolate old mux select bits
3807 or r16, r25, r25 // create new bc_ctl
3812 //orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
3814 mfpr r16, pt_impure
3815 lda r16, CNS_Q_IPR(r16)
3816 SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
3880 ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
3882 srl r16, osfpcb_v_pme, r16 // get pme bit
3884 and r16, 1, r16 // isolate pme bit
3889 sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position
3893 bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
3951 cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr
4068 mov r16, r0
4071 and r16, 63, r8
4080 ldf f17, 0(r16)
4081 stf f17, 0(r16)
4083 addq r16, 64, r16
4090 xor r17, r16, r9
4092 and r16, 7, r10
4095 ldq_u r9, 0(r16)
4106 stq_u r8, 0(r16)
4109 lda r16,8(r16)
4114 stq_u r8, 0(r16)
4118 ldq_u r9, 0(r16)
4121 stq_u r10, 0(r16)
4128 and r16, 7, r10
4135 insql r12, r16, r12
4136 ldq_u r13, 0(r16)
4137 mskql r13, r16, r13
4139 stq_u r12, 0(r16)
4140 addq r16, r10, r16
4156 stq r13, 0(r16)
4157 lda r16, 8(r16)
4165 stq r13, 0(r16)
4166 lda r16, 8(r16)
4176 stq_u r8, 0(r16)
4183 insqh r8, r16, r9
4184 insql r8, r16, r8
4188 insqh r12, r16, r13
4189 insql r12, r16, r12
4190 addq r16, r18, r10
4191 ldq_u r14, 0(r16)
4200 stq_u r8, 0(r16)