Lines Matching refs:r0
146 // r0 = whami
949 mtpr r0, pt0
955 bsr r0, pal_update_pcb // update the pcb
957 lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
1232 sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit
1233 or r2, r0, r2 // set the bit
1248 or r31, r31, r0 // set status to success
1254 addq r0, 1, r0 // set unknown pal or not loaded
1676 // r0 - return linkage
1694 ret r31, (r0)
1707 // pt0 = r0
1714 // r0 = halt_code
1739 // Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0)
1745 //orig store_reg1 hlt, r0, r1, ipr=1
1746 SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code
1748 mfpr r0, pt0 // get r0 back //orig
1749 //orig store_reg1 0, r0, r1 // save r0
1750 SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0
1752 mfpr r0, pt4 // get r1 back //orig
1753 //orig store_reg1 1, r0, r1 // save r1
1754 SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1
1759 mfpr r0, pt5 // get r3 back //orig
1760 //orig store_reg1 3, r0, r1 // save r3
1761 SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3
1764 // r0 has been saved
1775 ldah r0, (1<<(icsr_v_sde-16))(r31)
1776 bic r2, r0, r0 // ICSR with SDE clear
1777 mtpr r0, icsr // Turn off SDE
1936 mfpr r0, icsr // get icsr
1939 or r2, r0, r0 // set FEN on
1940 mtpr r0, icsr // write to icsr, enabling FEN
1944 srl r1, va_s_off, r0 // Clean off byte-within-page offset
1945 sll r0, pte_v_pfn, r0 // Shift to form PFN
1946 lda r0, pte_m_prot(r0) // Set all read/write enable bits
1947 mtpr r0, dtbPte // Load the PTE and set valid
1953 srl r4, va_s_off, r0 // Clean off byte-within-page offset
1954 sll r0, pte_v_pfn, r0 // Shift to form PFN
1955 lda r0, pte_m_prot(r0) // Set all read/write enable bits
1956 mtpr r0, dtbPte // Load the PTE and set valid
2016 //orig lda r0, cns_mchksize(r31) // get size of mchk area
2017 //orig store_reg1 mchkflag, r0, r1, ipr=1
2022 lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area
2023 SAVE_SHADOW(r0,CNS_Q_MCHK,r1);
2026 //orig or r31, 1, r0 // get a one
2027 //orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag
2032 or r31, 1, r0 // get a one
2033 SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag
2072 srl r1, va_s_off, r0 // Clean off byte-within-page offset
2073 sll r0, pte_v_pfn, r0 // Shift to form PFN
2074 lda r0, pte_m_prot(r0) // Set all read/write enable bits
2075 mtpr r0, dtbPte // Load the PTE and set valid
2081 srl r4, va_s_off, r0 // Clean off byte-within-page offset
2082 sll r0, pte_v_pfn, r0 // Shift to form PFN
2083 lda r0, pte_m_prot(r0) // Set all read/write enable bits
2084 mtpr r0, dtbPte // Load the PTE and set valid
2088 mfpr r0, icsr // Get current ICSR
2092 bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE>
2093 mtpr r0, icsr // Update the chip
2182 //orig mtpr r0, dtb_cm // set current mode in mbox too
2184 //orig srl r0, itb_asn_v_asn, r0
2185 //orig sll r0, dtb_asn_v_asn, r0
2186 //orig mtpr r0, dtb_asn // set ASN in Mbox too
2188 //orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr
2200 // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag)
2205 mtpr r0, dtbCm // Set Mbox current mode too.
2207 srl r0, 4, r0
2208 sll r0, 57, r0
2209 mtpr r0, dtbAsn // Set Mbox ASN too
2211 mtpr r0, mVptBr // Set Mbox VptBr too
2241 mfpr r0, icsr // Get icsr
2243 bic r0, r2, r2 // ICSR with SDE clear
2255 // Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ...
2319 RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1)
2339 // pt0 - saved r0
2381 mtpr r0, pt0 // Stash for scratch
2425 mtpr r0, pt0
2428 bsr r0, pal_update_pcb // update the pcb
2429 lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
2519 // option selector in r0
2550 cmpule r16, 255, r0 // see if a kibble was passed
2551 cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59)
2554 blbc r0, swppal_cont // nope, try it as an address
2556 cmpeq r16, 2, r0 // is it our friend OSF?
2557 blbc r0, swppal_fail // nope, don't know this fellow
2575 cmpeq r2, 0, r0 //
2577 blbc r0, swppal_fail // return unknown if bad bit set.
2632 mfpr r0, pt_mces // Read from PALtemp
2633 and r0, mces_m_all, r0 // Clear other bits
2865 mfpr r0, pt_pcbb // get pcbb
2873 stq_p r30, osfpcb_q_ksp(r0) // store old ksp
2877 stq_p r24, osfpcb_q_usp(r0) // store usp
2880 stl_p r25, osfpcb_l_cc(r0) // save time
2914 // v0 (r0) <- sysvalue
2920 mfpr r0, pt_sysval
2993 // v0 (r0) <- PS<IPL>
3005 bis r11, r31, r0 // return old ipl
3022 // v0 (r0) <- ps
3027 bis r11, r31, r0 // Fetch PALshadow PS
3079 // returned status in r0
3108 // r0 = value (same format as ev5 pmctr)
3146 cmpeq r16, 1, r0 // check for enable
3147 bne r0, perfmon_en // br if requested to enable
3149 cmpeq r16, 2, r0 // check for mux ctl
3150 bne r0, perfmon_muxctl // br if request to set mux controls
3152 cmpeq r16, 3, r0 // check for options
3153 bne r0, perfmon_ctl // br if request to set options
3155 cmpeq r16, 4, r0 // check for interrupt frequency select
3156 bne r0, perfmon_freq // br if request to change frequency select
3158 cmpeq r16, 5, r0 // check for counter read request
3159 bne r0, perfmon_rd // br if request to read counters
3161 cmpeq r16, 6, r0 // check for counter write request
3162 bne r0, perfmon_wr // br if request to write counters
3164 cmpeq r16, 7, r0 // check for counter clear/enable request
3165 bne r0, perfmon_enclr // br if request to clear/enable counters
3177 // v0 (r0) <- usp
3183 mfpr r0, pt_usp
3198 // v0 (r0) <- whami
3203 mfpr r0, pt_whami // Get Whami
3204 extbl r0, 1, r0 // Isolate just whami bits
3566 // v0 (r0) <- unique
3572 mfpr r0, pt_pcbb // get pcb pointer
3573 ldq_p r0, osfpcb_q_unique(r0) // get new value
3788 mfpr r0, ev5__pmctr
3789 bic r0, r8, r0 // clear old mux select bits
3790 or r0,r25, r25 // or in new mux select bits
3983 mfpr r0, ev5__pmctr
3985 bic r0, r8, r0 // clear old mode bits
3986 or r0, r25, r25 // or in new mode bits
4034 mfpr r0, ev5__pmctr
4035 or r0, 1, r0 // or in return status
4055 or r31, 1, r0 // set success
4059 or r31, r31, r0 // set fail
4068 mov r16, r0