sim_tests/cycle_dw8051_demo/cycle_model.cpp

66 //              |\- write back data  <
67 //              |                     \write data mem
73 // so these memory accesses are just read and write in internal memory
1092       mem_ale.write(0);
1093       mem_wr_n.write(1);
1094       mem_pswr_n.write(1);
1095       mem_rd_n.write(1);
1096       mem_psrd_n.write(1);
1097       p0_mem_reg_n.write(0);
1098       p0_addr_data_n.write(0);
1117       mem_ale.write(1);
1118       mem_wr_n.write(1);
1119       mem_pswr_n.write(1);
1120       mem_rd_n.write(1);
1121       mem_psrd_n.write(1);
1122       p0_mem_reg_n.write(0);
1123       p0_addr_data_n.write(0);
1126 	mem_data_out.write( sc_bv<8>( data ) );
1127 	p0_mem_reg_n.write(1);
1128 	p0_addr_data_n.write(1);
1139 	mem_addr.write( sc_bv<16>( addr & 0x0000ffff ) );
1140 	p0_mem_reg_n.write(1);
1141 	p0_addr_data_n.write(1);
1142 	p2_mem_reg_n.write(1);
1146 	mem_addr.write( sc_bv<16>( addr & 0x0000ffff ) );
1147 	p0_addr_data_n.write(0);
1148 	p2_mem_reg_n.write(1);
1159       mem_ale.write(0);
1169 	p0_mem_reg_n.write(0);
1170 	p0_addr_data_n.write(0);
1173 	  mem_rd_n.write(0); // read RAM
1178 	  mem_wr_n.write(0); // write RAM
1196 	  mem_rd_n.write(0); // read RAM
1203 	  mem_wr_n.write(0); // write RAM
1214       // read/write enable <- 1 when stretch>0
1221 	  mem_rd_n.write(1); // read RAM
1227 	  // reset write enable
1228 	  mem_wr_n.write(1); // write RAM
1248 	  mem_rd_n.write(1);
1254 	  mem_wr_n.write(1);
1454 //    write the value into the operand
1468     printf("write R%d <- %d\n",op->val,R[op->val]);
1474     // write address
1515 //        - write the data back in the destination
1615   // write back --------------------------------------------------------
1735   mem_ale.write(0);
1736   mem_wr_n.write(1);
1737   mem_pswr_n.write(1);
1738   mem_rd_n.write(1);
1739   mem_psrd_n.write(1);
1740   p0_mem_reg_n.write(0);
1741   p0_addr_data_n.write(0);