Lines Matching refs:sample
238 m_outstandReqHist.sample(m_outstanding_count);
317 m_latencyHist.sample(cycles);
318 m_typeLatencyHist[type]->sample(cycles);
321 m_missLatencyHist.sample(cycles);
322 m_missTypeLatencyHist[type]->sample(cycles);
325 m_missMachLatencyHist[respondingMach]->sample(cycles);
326 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
333 m_IssueToInitialDelayHist[respondingMach]->sample(
335 m_InitialToForwardDelayHist[respondingMach]->sample(
337 m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
339 m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
346 m_hitLatencyHist.sample(cycles);
347 m_hitTypeLatencyHist[type]->sample(cycles);
350 m_hitMachLatencyHist[respondingMach]->sample(cycles);
351 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);