Lines Matching refs:AbstractController
41 #include "mem/ruby/slicc_interface/AbstractController.hh"
51 AbstractController::AbstractController(const Params *p)
70 AbstractController::init()
82 AbstractController::resetStats()
92 AbstractController::regStats()
103 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
111 AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
125 AbstractController::wakeUpBuffers(Addr addr)
146 AbstractController::wakeUpAllBuffers(Addr addr)
167 AbstractController::wakeUpAllBuffers()
206 AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
213 AbstractController::isBlocked(Addr addr) const
219 AbstractController::unblock(Addr addr)
228 AbstractController::isBlocked(Addr addr)
234 AbstractController::getPort(const std::string &if_name, PortID idx)
240 AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
264 AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
289 AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
307 AbstractController::functionalMemoryRead(PacketPtr pkt)
313 AbstractController::functionalMemoryWrite(PacketPtr pkt)
328 AbstractController::recvTimingResp(PacketPtr pkt)
360 AbstractController::recvAtomic(PacketPtr pkt)
366 AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
374 AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
380 AbstractController::MemoryPort::MemoryPort(const std::string &_name,
381 AbstractController *_controller,