src/mem/drampower.cc

79     Data::MemTimingSpec timingSpec;
80     timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
81     timingSpec.RCD = divCeil(p->tRCD, p->tCK);
82     timingSpec.RL = divCeil(p->tCL, p->tCK);
83     timingSpec.RP = divCeil(p->tRP, p->tCK);
84     timingSpec.RFC = divCeil(p->tRFC, p->tCK);
85     timingSpec.RAS = divCeil(p->tRAS, p->tCK);
88     timingSpec.WL = timingSpec.RL - 1;
89     timingSpec.DQSCK = 0; // ignore for now
90     timingSpec.RTP = divCeil(p->tRTP, p->tCK);
91     timingSpec.WR = divCeil(p->tWR, p->tCK);
92     timingSpec.XP = divCeil(p->tXP, p->tCK);
93     timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK);
94     timingSpec.XS = divCeil(p->tXS, p->tCK);
95     timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK);
98     timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
99     assert(timingSpec.clkPeriod != 0);
100     timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
101     return timingSpec;