src/mem/dram_ctrl.hh

164      * column (read/write) command, when can it be precharged, and
199      * the DRAM and interacts with the bus read/write state machine,
396          * Track number of packets in read queue going to this rank
484          * Exit if there are any read entries regardless of the bus state.
650         const bool read;
668          * incoming read packets with packets in the write queue.
687          * QoS value of the encapsulated packet read at queuing time
722          * Return true if its a read packet
725         inline bool isRead() const { return read; }
731         inline bool isWrite() const { return !read; }
739               read(is_read), rank(_rank), bank(_bank), row(_row),
763      * Check if the read queue has room for more entries
765      * @param pktCount The number of entries needed in the read queue
766      * @return true if read queue is full, false otherwise
779      * When a new read comes in, first check if the write q has a
782      * "dram_pkt", and push them to the back of the read queue.\
784      * read request in the system, schedule an event to start
839      * @param isRead Is the request for a read or a write to DRAM
853      * @param extra_col_delay Any extra delay due to a read/write switch
860      * For FR-FCFS policy reorder the read/write queue depending on row buffer
864      * @param extra_col_delay Any extra delay due to a read/write switch
925      * The controller's main read and write queues, with support for QoS reordering
940      * Response queue where read packets wait after we're done working
944      * as sizing the read queue, this and the main read queue need to
1020      * Max column accesses (read and write) per row, before forcefully
1080     // per-master bytes read and written to memory
1084     // per-master bytes read and written to memory rate
1088     // per-master read and write serviced memory accesses
1092     // per-master read and write total memory access latency