src/mem/dram_ctrl.hh

113         MemoryPort(const std::string& name, DRAMCtrl& _memory);
123         virtual AddrRangeList getAddrRanges() const;
175         static const uint32_t NO_ROW = -1;
445         Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
447         const std::string name() const
471         bool inRefIdleState() const { return refreshState == REF_IDLE; }
480         bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
492         bool forceSelfRefreshExit() const {
503         bool isQueueEmpty() const;
620         const unsigned int burstCount;
639         const Tick entryTime;
645         const PacketPtr pkt;
648         const MasterID _masterId;
650         const bool read;
653         const uint8_t rank;
654         const uint8_t bank;
655         const uint32_t row;
662         const uint16_t bankId;
695         inline void qosValue(const uint8_t qv) { _qosValue = qv; }
701         inline uint8_t qosValue() const { return _qosValue; }
707         inline MasterID masterId() const { return _masterId; }
713         inline unsigned int getSize() const { return size; }
719         inline Addr getAddr() const { return addr; }
725         inline bool isRead() const { return read; }
731         inline bool isWrite() const { return !read; }
768     bool readQueueFull(unsigned int pktCount) const;
776     bool writeQueueFull(unsigned int pktCount) const;
842     DRAMPacket* decodeAddr(const PacketPtr pkt, Addr dramPktAddr,
843                            unsigned int size, bool isRead) const;
881     minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
913     void printQs() const;
922     Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
960     const uint32_t deviceSize;
961     const uint32_t deviceBusWidth;
962     const uint32_t burstLength;
963     const uint32_t deviceRowBufferSize;
964     const uint32_t devicesPerRank;
965     const uint32_t burstSize;
966     const uint32_t rowBufferSize;
967     const uint32_t columnsPerRowBuffer;
968     const uint32_t columnsPerStripe;
969     const uint32_t ranksPerChannel;
970     const uint32_t bankGroupsPerRank;
971     const bool bankGroupArch;
972     const uint32_t banksPerRank;
973     const uint32_t channels;
975     const uint32_t readBufferSize;
976     const uint32_t writeBufferSize;
977     const uint32_t writeHighThreshold;
978     const uint32_t writeLowThreshold;
979     const uint32_t minWritesPerSwitch;
987     const Tick M5_CLASS_VAR_USED tCK;
988     const Tick tRTW;
989     const Tick tCS;
990     const Tick tBURST;
991     const Tick tCCD_L_WR;
992     const Tick tCCD_L;
993     const Tick tRCD;
994     const Tick tCL;
995     const Tick tRP;
996     const Tick tRAS;
997     const Tick tWR;
998     const Tick tRTP;
999     const Tick tRFC;
1000     const Tick tREFI;
1001     const Tick tRRD;
1002     const Tick tRRD_L;
1003     const Tick tXAW;
1004     const Tick tXP;
1005     const Tick tXS;
1006     const uint32_t activationLimit;
1007     const Tick rankToRankDly;
1008     const Tick wrToRdDly;
1009     const Tick rdToWrDly;
1023     const uint32_t maxAccessesPerRow;
1030     const Tick frontendLatency;
1037     const Tick backendLatency;
1170     static bool sortTime(const Command& cmd, const Command& cmd_next) {
1178     DRAMCtrl(const DRAMCtrlParams* p);
1182     Port &getPort(const std::string &if_name,
1198     bool allRanksDrained() const;