Lines Matching refs:dram_pkt
475 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
476 dram_pkt->burstHelper = burst_helper;
483 readQueue[dram_pkt->qosValue()].push_back(dram_pkt);
485 ++dram_pkt->rankRef.readEntries;
489 dram_pkt->addr, 1);
542 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
549 writeQueue[dram_pkt->qosValue()].push_back(dram_pkt);
554 dram_pkt->addr, 1);
562 ++dram_pkt->rankRef.writeEntries;
685 DRAMPacket* dram_pkt = respQueue.front();
690 --dram_pkt->rankRef.readEntries;
692 dram_pkt->rank, dram_pkt->rankRef.readEntries);
696 assert(dram_pkt->rankRef.outstandingEvents > 0);
698 --dram_pkt->rankRef.outstandingEvents;
701 assert((dram_pkt->rankRef.pwrState != PWR_SREF) &&
702 (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) &&
703 (dram_pkt->rankRef.pwrState != PWR_ACT_PDN));
707 if (dram_pkt->rankRef.isQueueEmpty() &&
708 dram_pkt->rankRef.outstandingEvents == 0 && enableDRAMPowerdown) {
710 assert(!dram_pkt->rankRef.activateEvent.scheduled());
711 assert(!dram_pkt->rankRef.prechargeEvent.scheduled());
716 "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState);
721 if (dram_pkt->rankRef.pwrState == PWR_IDLE) {
725 dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick());
728 if (dram_pkt->burstHelper) {
730 dram_pkt->burstHelper->burstsServiced++;
731 if (dram_pkt->burstHelper->burstsServiced ==
732 dram_pkt->burstHelper->burstCount) {
737 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
738 delete dram_pkt->burstHelper;
739 dram_pkt->burstHelper = NULL;
743 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
781 DRAMPacket* dram_pkt = *(queue.begin());
782 if (ranks[dram_pkt->rank]->inRefIdleState()) {
791 DRAMPacket* dram_pkt = *i;
792 if (ranks[dram_pkt->rank]->inRefIdleState()) {
838 DRAMPacket* dram_pkt = *i;
839 const Bank& bank = dram_pkt->bankRef;
840 const Tick col_allowed_at = dram_pkt->isRead() ? bank.rdAllowedAt :
844 __func__, dram_pkt->bankRef.bank);
848 if (dram_pkt->rankRef.inRefIdleState()) {
852 dram_pkt->bankRef.bank, dram_pkt->rankRef.rank);
855 if (bank.openRow == dram_pkt->row) {
890 if (bits(earliest_banks[dram_pkt->rank],
891 dram_pkt->bank, dram_pkt->bank)) {
905 dram_pkt->bankRef.bank, dram_pkt->rankRef.rank);
1103 DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
1106 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
1109 Rank& rank = dram_pkt->rankRef;
1120 Bank& bank = dram_pkt->bankRef;
1126 if (bank.openRow == dram_pkt->row) {
1142 activateBank(rank, bank, act_tick, dram_pkt->row);
1146 const Tick col_allowed_at = dram_pkt->isRead() ?
1154 dram_pkt->readyTime = cmd_at + tCL + tBURST;
1165 if (dram_pkt->rank == j) {
1173 dly_to_rd_cmd = dram_pkt->isRead() ?
1175 dly_to_wr_cmd = dram_pkt->isRead() ?
1180 dly_to_rd_cmd = dram_pkt->isRead() ? tBURST : wrToRdDly;
1181 dly_to_wr_cmd = dram_pkt->isRead() ? rdToWrDly : tBURST;
1198 activeRank = dram_pkt->rank;
1204 dram_pkt->isRead() ? cmd_at + tRTP :
1205 dram_pkt->readyTime + tWR);
1233 dram_pkt->isRead() ? readQueue : writeQueue;
1245 if (dram_pkt != (*p)) {
1246 bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
1247 (dram_pkt->bank == (*p)->bank);
1249 bool same_row = dram_pkt->row == (*p)->row;
1269 std::string mem_cmd = dram_pkt->isRead() ? "RD" : "WR";
1279 dram_pkt->addr, dram_pkt->readyTime, nextBurstAt);
1281 dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank,
1285 timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
1294 DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1304 if (dram_pkt->isRead()) {
1309 perBankRdBursts[dram_pkt->bankId]++;
1312 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
1313 masterReadTotalLat[dram_pkt->masterId()] +=
1314 dram_pkt->readyTime - dram_pkt->entryTime;
1317 totQLat += cmd_at - dram_pkt->entryTime;
1318 masterReadBytes[dram_pkt->masterId()] += dram_pkt->size;
1324 perBankWrBursts[dram_pkt->bankId]++;
1325 masterWriteBytes[dram_pkt->masterId()] += dram_pkt->size;
1326 masterWriteTotalLat[dram_pkt->masterId()] +=
1327 dram_pkt->readyTime - dram_pkt->entryTime;
1479 auto dram_pkt = *to_read;
1481 assert(dram_pkt->rankRef.inRefIdleState());
1483 doDRAMAccess(dram_pkt);
1486 ++dram_pkt->rankRef.outstandingEvents;
1488 assert(dram_pkt->size <= burstSize);
1489 assert(dram_pkt->readyTime >= curTick());
1493 dram_pkt->qosValue(), dram_pkt->getAddr(), 1,
1494 dram_pkt->readyTime - dram_pkt->entryTime);
1501 schedule(respondEvent, dram_pkt->readyTime);
1503 assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
1507 respQueue.push_back(dram_pkt);
1515 readQueue[dram_pkt->qosValue()].erase(to_read);
1561 auto dram_pkt = *to_write;
1563 assert(dram_pkt->rankRef.inRefIdleState());
1565 assert(dram_pkt->size <= burstSize);
1567 doDRAMAccess(dram_pkt);
1570 --dram_pkt->rankRef.writeEntries;
1578 if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) {
1579 schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime);
1581 ++dram_pkt->rankRef.outstandingEvents;
1583 } else if (dram_pkt->rankRef.writeDoneEvent.when() <
1584 dram_pkt->readyTime) {
1586 reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime);
1589 isInWriteQueue.erase(burstAlign(dram_pkt->addr));
1592 logResponse(MemCtrl::WRITE, dram_pkt->masterId(),
1593 dram_pkt->qosValue(), dram_pkt->getAddr(), 1,
1594 dram_pkt->readyTime - dram_pkt->entryTime);
1598 writeQueue[dram_pkt->qosValue()].erase(to_write);
1600 delete dram_pkt;