src/mem/dram_ctrl.cc

220             assert(columnsPerStripe >= 1);
235             assert(columnsPerStripe <= columnsPerRowBuffer);
395     assert(rank < ranksPerChannel);
396     assert(bank < banksPerRank);
397     assert(row < rowsPerBank);
398     assert(row < Bank::NO_ROW);
416     assert(!pkt->isWrite());
418     assert(pktCount != 0);
478             assert(!readQueueFull(1));
522     assert(pkt->isWrite());
544             assert(totalWriteQueueSize < writeBufferSize);
556             assert(totalWriteQueueSize == isInWriteQueue.size());
648         assert(size != 0);
661         assert(pkt->isRead());
662         assert(size != 0);
696     assert(dram_pkt->rankRef.outstandingEvents > 0);
701     assert((dram_pkt->rankRef.pwrState != PWR_SREF) &&
710         assert(!dram_pkt->rankRef.activateEvent.scheduled());
711         assert(!dram_pkt->rankRef.prechargeEvent.scheduled());
750         assert(respQueue.front()->readyTime >= curTick());
751         assert(!respondEvent.scheduled());
929         assert(pkt->isResponse());
957     assert(rank_ref.actTicks.size() == activationLimit);
962     assert(bank_ref.openRow == Bank::NO_ROW);
972     assert(rank_ref.numBanksActive <= banksPerRank);
1058     assert(bank.openRow != Bank::NO_ROW);
1073     assert(rank_ref.numBanksActive != 0);
1115         assert(rank.pwrState != PWR_SREF);
1481             assert(dram_pkt->rankRef.inRefIdleState());
1488             assert(dram_pkt->size <= burstSize);
1489             assert(dram_pkt->readyTime >= curTick());
1500                 assert(!respondEvent.scheduled());
1503                 assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
1504                 assert(respondEvent.scheduled());
1563         assert(dram_pkt->rankRef.inRefIdleState());
1565         assert(dram_pkt->size <= burstSize);
1673                 assert(ranks[i]->inRefIdleState());
1761     assert(ref_tick > curTick());
1850     assert(outstandingEvents > 0);
1862             assert(pwrState == PWR_ACT);
1881     assert(outstandingEvents > 0);
1986             assert(prechargeEvent.scheduled());
1990         assert(numBanksActive == 0);
2002         assert(numBanksActive == 0);
2003         assert(pwrState == PWR_REF);
2038         assert(numBanksActive == 0);
2039         assert(pwrState == PWR_REF);
2041         assert(!powerEvent.scheduled());
2053                 assert(pwrState == PWR_REF);
2064                 assert(outstandingEvents == 1);
2093     assert(tick >= curTick());
2143         assert(pwrStatePostRefresh == PWR_PRE_PDN);
2217     assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) ||
2234     assert(curTick() >= pwrStateTick);
2255         assert(outstandingEvents == 1);
2263             assert(pwrState == PWR_PRE_PDN);
2278         assert(prev_state == PWR_ACT_PDN);
2302                     assert(!powerEvent.scheduled());
2306                         assert(prev_state == PWR_PRE_PDN);
2315                     assert(prechargeEvent.scheduled());
2325         assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT);
2339             assert(outstandingEvents == 1);
2350             assert(!powerEvent.scheduled());