src/mem/dram_ctrl.cc

24  * neither the name of the copyright holders nor the names of its
64     port(name() + ".port", *this), isTimingMode(false),
66     nextReqEvent([this]{ processNextReqEvent(); }, name()),
67     respondEvent([this]{ processRespondEvent(); }, name()),
194         fatal("DRAMCtrl %s is unconnected!\n", name());
204                   name(), range.stripes(), channels);
209                       "address map\n", name());
226                       "as the cache line size\n", name());
232                       "as the row-buffer size\n", name());
1730       writeDoneEvent([this]{ processWriteDoneEvent(); }, name()),
1731       activateEvent([this]{ processActivateEvent(); }, name()),
1732       prechargeEvent([this]{ processPrechargeEvent(); }, name()),
1733       refreshEvent([this]{ processRefreshEvent(); }, name()),
1734       powerEvent([this]{ processPowerEvent(); }, name()),
1735       wakeUpEvent([this]{ processWakeUpEvent(); }, name())
2436         .name(name() + ".memoryStateTime")
2446         .name(name() + ".actEnergy")
2450         .name(name() + ".preEnergy")
2454         .name(name() + ".readEnergy")
2458         .name(name() + ".writeEnergy")
2462         .name(name() + ".refreshEnergy")
2466         .name(name() + ".actBackEnergy")
2470         .name(name() + ".preBackEnergy")
2474         .name(name() + ".actPowerDownEnergy")
2478         .name(name() + ".prePowerDownEnergy")
2482         .name(name() + ".selfRefreshEnergy")
2486         .name(name() + ".totalEnergy")
2490         .name(name() + ".averagePower")
2494         .name(name() + ".totalIdleTime")
2514         .name(name() + ".readReqs")
2518         .name(name() + ".writeReqs")
2522         .name(name() + ".readBursts")
2527         .name(name() + ".writeBursts")
2532         .name(name() + ".servicedByWrQ")
2536         .name(name() + ".mergedWrBursts")
2540         .name(name() + ".neitherReadNorWriteReqs")
2545         .name(name() + ".perBankRdBursts")
2550         .name(name() + ".perBankWrBursts")
2554         .name(name() + ".avgRdQLen")
2559         .name(name() + ".avgWrQLen")
2564         .name(name() + ".totQLat")
2568         .name(name() + ".totBusLat")
2572         .name(name() + ".totMemAccLat")
2577         .name(name() + ".avgQLat")
2584         .name(name() + ".avgBusLat")
2591         .name(name() + ".avgMemAccLat")
2598         .name(name() + ".numRdRetry")
2602         .name(name() + ".numWrRetry")
2606         .name(name() + ".readRowHits")
2610         .name(name() + ".writeRowHits")
2614         .name(name() + ".readRowHitRate")
2621         .name(name() + ".writeRowHitRate")
2629         .name(name() + ".readPktSize")
2634         .name(name() + ".writePktSize")
2639         .name(name() + ".rdQLenPdf")
2644         .name(name() + ".wrQLenPdf")
2649          .name(name() + ".bytesPerActivate")
2655          .name(name() + ".rdPerTurnAround")
2661          .name(name() + ".wrPerTurnAround")
2666         .name(name() + ".bytesReadDRAM")
2670         .name(name() + ".bytesReadWrQ")
2674         .name(name() + ".bytesWritten")
2678         .name(name() + ".bytesReadSys")
2682         .name(name() + ".bytesWrittenSys")
2686         .name(name() + ".avgRdBW")
2693         .name(name() + ".avgWrBW")
2700         .name(name() + ".avgRdBWSys")
2707         .name(name() + ".avgWrBWSys")
2714         .name(name() + ".peakBW")
2721         .name(name() + ".busUtil")
2727         .name(name() + ".totGap")
2731         .name(name() + ".avgGap")
2739         .name(name() + ".busUtilRead")
2746         .name(name() + ".busUtilWrite")
2753         .name(name() + ".pageHitRate")
2763         .name(name() + ".masterReadBytes")
2769         .name(name() + ".masterWriteBytes")
2774     masterReadRate.name(name() + ".masterReadRate")
2782         .name(name() + ".masterWriteRate")
2791         .name(name() + ".masterReadAccesses")
2797         .name(name() + ".masterWriteAccesses")
2804         .name(name() + ".masterReadTotalLat")
2808     masterReadAvgLat.name(name() + ".masterReadAvgLat")
2817         .name(name() + ".masterWriteTotalLat")
2821     masterWriteAvgLat.name(name() + ".masterWriteAvgLat")
2928 DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
2929     : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this, true),
2944     pkt->pushLabel(memory.name());