src/mem/dram_ctrl.cc

124     // determine the rows per bank by looking at the total capacity
151     // basic bank group architecture checks ->
153         // must have at least one bank per bank group
159         // must have same number of banks in each bank group
161             fatal("Banks per rank (%d) must be evenly divisible by bank groups "
162                   "per rank (%d) for equal banks per bank group\n",
168                   "bank groups per rank (%d) is greater than 1\n",
174                   "bank groups per rank (%d) is greater than 1\n",
177         // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
181                   "bank groups per rank (%d) is greater than 1\n",
310     // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
313     uint8_t bank;
319     // a specific column, row, bank, rank and channel
332         // after the channel bits, get the bank bits to interleave
334         bank = addr % banksPerRank;
337         // after the bank, we get the rank bits which thus interleaves
354         // after the column bits, we get the bank bits to interleave
356         bank = addr % banksPerRank;
359         // after the bank, we get the rank bits which thus interleaves
378         // start with the bank bits, as this provides the maximum
380         bank = addr % banksPerRank;
396     assert(bank < banksPerRank);
401             dramPktAddr, rank, bank, row);
406     uint16_t bank_id = banksPerRank * rank + bank;
407     return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
408                           size, ranks[rank]->banks[bank], *ranks[rank]);
819     // without incurring additional bus delay due to bank timing
824     // remember if we found a row hit, not seamless, but bank prepped
839         const Bank& bank = dram_pkt->bankRef;
840         const Tick col_allowed_at = dram_pkt->isRead() ? bank.rdAllowedAt :
841                                                          bank.wrAllowedAt;
843         DPRINTF(DRAM, "%s checking packet in bank %d\n",
844                 __func__, dram_pkt->bankRef.bank);
851                     "%s bank %d - Rank %d available\n", __func__,
852                     dram_pkt->bankRef.bank, dram_pkt->rankRef.rank);
855             if (bank.openRow == dram_pkt->row) {
856                 // no additional rank-to-rank or same bank-group
863                     // and/or different bank-group accesses
870                     // issue the bank commands without incurring delay, and
878                 // if we have not initialised the bank status, do it
881                     // determine entries with earliest bank delay
887                 // bank is amongst first available banks
891                          dram_pkt->bank, dram_pkt->bank)) {
896                     // bank commands 'behind the scenes'
904             DPRINTF(DRAM, "%s bank %d - Rank %d not available\n", __func__,
905                     dram_pkt->bankRef.bank, dram_pkt->rankRef.rank);
974     DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
975             bank_ref.bank, rank_ref.rank, act_tick,
978     rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank,
982             timeStampOffset, bank_ref.bank, rank_ref.rank);
984     // The next access has to respect tRAS for this bank
993         // next activate to any bank in this rank must not happen
996             // bank group architecture requires longer delays between
997             // ACT commands within the same bank group.  Use tRRD_L
1003             // 1) bank group architecture is not supportted
1004             // 2) bank is in a different bank group
1055 DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace)
1057     // make sure the bank has an open row
1058     assert(bank.openRow != Bank::NO_ROW);
1062     bytesPerActivate.sample(bank.bytesAccessed);
1064     bank.openRow = Bank::NO_ROW;
1067     bank.preAllowedAt = pre_at;
1071     bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
1076     DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
1077             "%d active\n", bank.bank, rank_ref.rank, pre_at,
1082         rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank,
1085                 timeStampOffset, bank.bank, rank_ref.rank);
1105     DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1106             dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
1119     // get the bank
1120     Bank& bank = dram_pkt->bankRef;
1125     // Determine the access latency and update the bank state
1126     if (bank.openRow == dram_pkt->row) {
1132         if (bank.openRow != Bank::NO_ROW) {
1133             prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick()));
1138         Tick act_tick = std::max(bank.actAllowedAt, curTick());
1142         activateBank(rank, bank, act_tick, dram_pkt->row);
1147                                           bank.rdAllowedAt : bank.wrAllowedAt;
1157     // bank (add a max with tCCD/tCCD_L/tCCD_L_WR here)
1162             // next burst to same bank group in this rank must not happen
1163             // before tCCD_L.  Different bank group timing requirement is
1167                    (bank.bankgr == ranks[j]->banks[i].bankgr)) {
1168                     // bank group architecture requires longer delays between
1169                     // RD/WR burst commands to the same bank group.
1184                 // different rank is by default in a different bank group and
1203     bank.preAllowedAt = std::max(bank.preAllowedAt,
1208     bank.bytesAccessed += burstSize;
1209     ++bank.rowAccesses;
1213         bank.rowAccesses == maxAccessesPerRow;
1223         // are bank conflicts in the queue
1240             // 2) if no hit is found, got_bank_conflict is set to true if a bank
1247                                           (dram_pkt->bank == (*p)->bank);
1262         //    have a bank conflict
1281     dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank,
1285             timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
1292         prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt));
1294         DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1651     // Flag condition when bank can be opened without incurring additional
1656     // bank in question
1663     // Find command with optimal bank timing
1669             // if we have waiting requests for the bank, and it is
1674                 // simplistic approximation of when the bank can issue
1687                 // bank can issue burst back-to-back (seamlessly) with
1691                 // if we found a new seamless bank or we have no
1692                 // seamless banks, and got a bank with an earlier
1696                     // if we did not have a seamless bank before, and
1697                     // we do now, reset the bank mask, also reset it
1698                     // if we have not yet found a seamless bank and
1711                     // set the bit corresponding to the available bank
1738         banks[b].bank = b;
1740         // Here we assume that all DRAM generations address bank groups as
1743             // Simply assign lower bits to bank group in order to
1744             // rotate across bank groups as banks are incremented
1745             // e.g. with 4 banks per bank group and 16 banks total:
1746             //    banks 0,4,8,12  are in bank group 0
1747             //    banks 1,5,9,13  are in bank group 1
1748             //    banks 2,6,10,14 are in bank group 2
1749             //    banks 3,7,11,15 are in bank group 3
1752             // No bank groups; simply assign to bank number
1820              power.powerlib.doCommand(cmd.type, cmd.bank,
1838     // we should transition to the active state as soon as any bank is active
1861             // should still be in ACT state since bank still open
1869             // we should transition to the idle state when the last bank
1939         // precharge any active bank
1942             // only a single bank open
1949                 // respect both causality and any existing bank
2183         // respect both causality and any existing bank
2546         .desc("Per bank write bursts");
2551         .desc("Per bank write bursts");