mem/cache/cache_blk.hh

141         bool matches(const RequestPtr &req) const
143             Addr req_low = req->getPaddr();
144             Addr req_high = req_low + req->getSize() -1;
145             return (contextId == req->contextId()) &&
150         bool intersects(const RequestPtr &req) const
152             Addr req_low = req->getPaddr();
153             Addr req_high = req_low + req->getSize() - 1;
158         Lock(const RequestPtr &req)
159             : contextId(req->contextId()),
160               lowAddr(req->getPaddr()),
161               highAddr(lowAddr + req->getSize() - 1)
316             if (l->intersects(pkt->req))
322         lockList.emplace_front(pkt->req);
329     void clearLoadLocks(const RequestPtr &req)
333             if (l->intersects(req) && l->contextId != req->contextId()) {
402         const RequestPtr &req = pkt->req;
411                 if (l->matches(pkt->req)) {
422             req->setExtraData(success ? 1 : 0);
425             clearLoadLocks(req);
431             clearLoadLocks(req);