Lines Matching refs:PacketPtr
88 void promoteWholeLineWrites(PacketPtr pkt);
90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
93 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
96 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
100 void recvTimingReq(PacketPtr pkt) override;
106 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
109 void recvTimingSnoopReq(PacketPtr pkt) override;
111 void recvTimingSnoopResp(PacketPtr pkt) override;
113 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
116 Tick recvAtomic(PacketPtr pkt) override;
118 Tick recvAtomicSnoop(PacketPtr pkt) override;
120 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
124 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
139 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
142 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
150 PacketPtr cleanEvictBlk(CacheBlk *blk);
152 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
160 bool isCachedAbove(PacketPtr pkt, bool is_timing = true);