Lines Matching refs:Stats

923     Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
925 Stats::Formula demandHits;
927 Stats::Formula overallHits;
931 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
933 Stats::Formula demandMisses;
935 Stats::Formula overallMisses;
941 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
943 Stats::Formula demandMissLatency;
945 Stats::Formula overallMissLatency;
948 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
950 Stats::Formula demandAccesses;
952 Stats::Formula overallAccesses;
955 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
957 Stats::Formula demandMissRate;
959 Stats::Formula overallMissRate;
962 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
964 Stats::Formula demandAvgMissLatency;
966 Stats::Formula overallAvgMissLatency;
969 Stats::Vector blocked_cycles;
971 Stats::Vector blocked_causes;
974 Stats::Formula avg_blocked;
977 Stats::Scalar unusedPrefetches;
980 Stats::Vector writebacks;
983 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
985 Stats::Formula demandMshrHits;
987 Stats::Formula overallMshrHits;
990 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
992 Stats::Formula demandMshrMisses;
994 Stats::Formula overallMshrMisses;
997 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
999 Stats::Formula overallMshrUncacheable;
1002 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
1004 Stats::Formula demandMshrMissLatency;
1006 Stats::Formula overallMshrMissLatency;
1009 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
1011 Stats::Formula overallMshrUncacheableLatency;
1014 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
1016 Stats::Formula demandMshrMissRate;
1018 Stats::Formula overallMshrMissRate;
1021 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
1023 Stats::Formula demandAvgMshrMissLatency;
1025 Stats::Formula overallAvgMshrMissLatency;
1028 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
1030 Stats::Formula overallAvgMshrUncacheableLatency;
1033 Stats::Scalar replacements;
1036 Stats::Scalar dataExpansions;