Lines Matching defs:port
118 * A cache master port is used for the memory-side port of the
119 * cache, and in addition to the basic timing port that only sends
123 * and the sendDeferredPacket of the timing port is modified to
150 * Memory-side port always snoops.
159 * the memory-side cache port to also send requests based on the
173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
176 ReqPacketQueue(cache, port, label), cache(cache),
209 * The memory-side port extends the base cache master port with
241 * A cache slave port is used for the CPU-side port of the cache,
242 * and it is basically a simple timing port that uses a transmit
244 * addition, it has the functionality to block the port for
245 * incoming requests. If blocked, the port will issue a retry once
282 * The CPU-side port extends the base cache slave port with access
577 * @param fromCpuSide from the CPU side port or the memory side port
870 /** Do we forward snoops from mem side port through to cpu side port? */
1165 * Schedule a send event for the memory-side port. If already
1167 * time. When the specified time is reached, the port is free to
1239 * @return True if the port is waiting for a retry
1249 * @return True if the port is waiting for a retry