mem/cache/base.cc

24  * neither the name of the copyright holders nor the names of its
81       cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
82       memSidePort(p->name + ".mem_side", this, "MemSidePort"),
92                                     name(), false,
184         fatal("Cache ports on %s are not connected\n", name());
411              "%s saw a non-zero packet delay\n", name());
631     pkt->pushLabel(name());
661     // We're leaving the cache, so pop cache->name() label
1032                   name());
1407                           "in read-only cache %s\n", name());
1890             .name(name() + "." + cstr + "_hits")
1911         .name(name() + ".demand_hits")
1921         .name(name() + ".overall_hits")
1937             .name(name() + "." + cstr + "_misses")
1947         .name(name() + ".demand_misses")
1957         .name(name() + ".overall_misses")
1973             .name(name() + "." + cstr + "_miss_latency")
1983         .name(name() + ".demand_miss_latency")
1993         .name(name() + ".overall_miss_latency")
2008             .name(name() + "." + cstr + "_accesses")
2020         .name(name() + ".demand_accesses")
2030         .name(name() + ".overall_accesses")
2045             .name(name() + "." + cstr + "_miss_rate")
2057         .name(name() + ".demand_miss_rate")
2067         .name(name() + ".overall_miss_rate")
2082             .name(name() + "." + cstr + "_avg_miss_latency")
2095         .name(name() + ".demand_avg_miss_latency")
2105         .name(name() + ".overall_avg_miss_latency")
2116         .name(name() + ".blocked_cycles")
2125         .name(name() + ".blocked")
2132         .name(name() + ".avg_blocked_cycles")
2141         .name(name() + ".unused_prefetches")
2148         .name(name() + ".writebacks")
2164             .name(name() + "." + cstr + "_mshr_hits")
2174         .name(name() + ".demand_mshr_hits")
2184         .name(name() + ".overall_mshr_hits")
2200             .name(name() + "." + cstr + "_mshr_misses")
2210         .name(name() + ".demand_mshr_misses")
2220         .name(name() + ".overall_mshr_misses")
2236             .name(name() + "." + cstr + "_mshr_miss_latency")
2246         .name(name() + ".demand_mshr_miss_latency")
2256         .name(name() + ".overall_mshr_miss_latency")
2273             .name(name() + "." + cstr + "_mshr_uncacheable")
2283         .name(name() + ".overall_mshr_uncacheable_misses")
2300             .name(name() + "." + cstr + "_mshr_uncacheable_latency")
2311         .name(name() + ".overall_mshr_uncacheable_latency")
2328             .name(name() + "." + cstr + "_mshr_miss_rate")
2341         .name(name() + ".demand_mshr_miss_rate")
2351         .name(name() + ".overall_mshr_miss_rate")
2366             .name(name() + "." + cstr + "_avg_mshr_miss_latency")
2380         .name(name() + ".demand_avg_mshr_miss_latency")
2390         .name(name() + ".overall_avg_mshr_miss_latency")
2405             .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
2419         .name(name() + ".overall_avg_mshr_uncacheable_latency")
2430         .name(name() + ".replacements")
2435         .name(name() + ".data_expansions")