Lines Matching refs:name
12 * neither the name of the copyright holders nor the names of its
42 memPort(params->name + ".mem_side", this),
47 // automatically created depending on the name of the vector port and
48 // holds the number of connections to this port name
50 cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i), i, this);
57 // This is the name from the Python SimObject declaration in SimpleCache.py
210 name() + ".accessEvent", true),
432 hits.name(name() + ".hits")
436 misses.name(name() + ".misses")
440 missLatency.name(name() + ".missLatency")
445 hitRatio.name(name() + ".hitRatio")