dev/x86/SouthBridge.py

70     ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
71     ide.BAR0 = 0x1f0
72     ide.BAR0LegacyIO = True
73     ide.BAR1 = 0x3f4
74     ide.BAR1Size = '3B'
75     ide.BAR1LegacyIO = True
76     ide.BAR2 = 0x170
77     ide.BAR2LegacyIO = True
78     ide.BAR3 = 0x374
79     ide.BAR3Size = '3B'
80     ide.BAR3LegacyIO = True
81     ide.BAR4 = 1
82     ide.Command = 0
83     ide.ProgIF = 0x80
84     ide.InterruptLine = 14
85     ide.InterruptPin = 1
86     ide.LegacyIOBase = x86IOAddress(0)
104         self.ide.pio = bus.master
105         if dma_ports.count(self.ide.dma) == 0:
106                 self.ide.dma = bus.slave