dev/net/sinicreg.hh

34 #define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
64 __SINIC_REG32(Config,        0x00) // 32: configuration register
65 __SINIC_REG32(Command,       0x04) // 32: command register
66 __SINIC_REG32(IntrStatus,    0x08) // 32: interrupt status
67 __SINIC_REG32(IntrMask,      0x0c) // 32: interrupt mask
68 __SINIC_REG32(RxMaxCopy,     0x10) // 32: max bytes per rx copy
69 __SINIC_REG32(TxMaxCopy,     0x14) // 32: max bytes per tx copy
70 __SINIC_REG32(ZeroCopySize,  0x18) // 32: bytes to copy if below threshold
71 __SINIC_REG32(ZeroCopyMark,  0x1c) // 32: only zero-copy above this threshold
72 __SINIC_REG32(VirtualCount,  0x20) // 32: number of virutal NICs
73 __SINIC_REG32(RxMaxIntr,     0x24) // 32: max receives per interrupt
74 __SINIC_REG32(RxFifoSize,    0x28) // 32: rx fifo capacity in bytes
75 __SINIC_REG32(TxFifoSize,    0x2c) // 32: tx fifo capacity in bytes
76 __SINIC_REG32(RxFifoLow,     0x30) // 32: rx fifo low watermark
77 __SINIC_REG32(TxFifoLow,     0x34) // 32: tx fifo low watermark
78 __SINIC_REG32(RxFifoHigh,    0x38) // 32: rx fifo high watermark
79 __SINIC_REG32(TxFifoHigh,    0x3c) // 32: tx fifo high watermark
80 __SINIC_REG32(RxData,        0x40) // 64: receive data
81 __SINIC_REG32(RxDone,        0x48) // 64: receive done
82 __SINIC_REG32(RxWait,        0x50) // 64: receive done (busy wait)
83 __SINIC_REG32(TxData,        0x58) // 64: transmit data
84 __SINIC_REG32(TxDone,        0x60) // 64: transmit done
85 __SINIC_REG32(TxWait,        0x68) // 64: transmit done (busy wait)
86 __SINIC_REG32(HwAddr,        0x70) // 64: mac address
87 __SINIC_REG32(RxStatus,      0x78)
88 __SINIC_REG32(Size,          0x80) // register addres space size
119 __SINIC_REG32(Intr_All,       0x01ff) // all valid interrupts
120 __SINIC_REG32(Intr_NoDelay,   0x01cc) // interrupts that aren't coalesced
121 __SINIC_REG32(Intr_Res,      ~0x01ff) // reserved interrupt bits