dev/net/ns_gige.cc

105       txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
939     assert(txDmaState == dmaIdle);
1005     if (txDmaState == dmaReadWaiting || txDmaState == dmaWriteWaiting)
1035     if (txDmaState == dmaReadWaiting || txDmaState == dmaWriteWaiting)
1410     assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
1411     txDmaState = dmaReading;
1414         txDmaState = dmaReadWaiting;
1424     assert(txDmaState == dmaReading);
1425     txDmaState = dmaIdle;
1441     assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
1442     txDmaState = dmaWriting;
1445         txDmaState = dmaWriteWaiting;
1454     assert(txDmaState == dmaWriting);
1455     txDmaState = dmaIdle;
1490     switch(txDmaState) {
1544         if (txDmaState != dmaIdle)
1551         if (txDmaState != dmaIdle)
1729         if (txDmaState != dmaIdle)
1741         if (txDmaState != dmaIdle)
1761             if (txDmaState != dmaIdle)
2133     int txDmaState = this->txDmaState;
2134     SERIALIZE_SCALAR(txDmaState);
2304     int txDmaState;
2305     UNSERIALIZE_SCALAR(txDmaState);
2306     this->txDmaState = (DmaState) txDmaState;