dev/net/i8254xGBe_defs.hh

40 const uint32_t REG_CTRL     = 0x00000;
41 const uint32_t REG_STATUS   = 0x00008;
42 const uint32_t REG_EECD     = 0x00010;
43 const uint32_t REG_EERD     = 0x00014;
44 const uint32_t REG_CTRL_EXT = 0x00018;
45 const uint32_t REG_MDIC     = 0x00020;
46 const uint32_t REG_FCAL     = 0x00028;
47 const uint32_t REG_FCAH     = 0x0002C;
48 const uint32_t REG_FCT      = 0x00030;
49 const uint32_t REG_VET      = 0x00038;
50 const uint32_t REG_PBA      = 0x01000;
51 const uint32_t REG_ICR      = 0x000C0;
52 const uint32_t REG_ITR      = 0x000C4;
53 const uint32_t REG_ICS      = 0x000C8;
54 const uint32_t REG_IMS      = 0x000D0;
55 const uint32_t REG_IMC      = 0x000D8;
56 const uint32_t REG_IAM      = 0x000E0;
57 const uint32_t REG_RCTL     = 0x00100;
58 const uint32_t REG_FCTTV    = 0x00170;
59 const uint32_t REG_TIPG     = 0x00410;
60 const uint32_t REG_AIFS     = 0x00458;
61 const uint32_t REG_LEDCTL   = 0x00e00;
62 const uint32_t REG_EICR     = 0x01580;
63 const uint32_t REG_IVAR0    = 0x01700;
64 const uint32_t REG_FCRTL    = 0x02160;
65 const uint32_t REG_FCRTH    = 0x02168;
66 const uint32_t REG_RDBAL    = 0x02800;
67 const uint32_t REG_RDBAH    = 0x02804;
68 const uint32_t REG_RDLEN    = 0x02808;
69 const uint32_t REG_SRRCTL   = 0x0280C;
70 const uint32_t REG_RDH      = 0x02810;
71 const uint32_t REG_RDT      = 0x02818;
72 const uint32_t REG_RDTR     = 0x02820;
73 const uint32_t REG_RXDCTL   = 0x02828;
74 const uint32_t REG_RADV     = 0x0282C;
75 const uint32_t REG_TCTL     = 0x00400;
76 const uint32_t REG_TDBAL    = 0x03800;
77 const uint32_t REG_TDBAH    = 0x03804;
78 const uint32_t REG_TDLEN    = 0x03808;
79 const uint32_t REG_TDH      = 0x03810;
80 const uint32_t REG_TXDCA_CTL = 0x03814;
81 const uint32_t REG_TDT      = 0x03818;
82 const uint32_t REG_TIDV     = 0x03820;
83 const uint32_t REG_TXDCTL   = 0x03828;
84 const uint32_t REG_TADV     = 0x0382C;
85 const uint32_t REG_TDWBAL   = 0x03838;
86 const uint32_t REG_TDWBAH   = 0x0383C;
87 const uint32_t REG_CRCERRS  = 0x04000;
88 const uint32_t REG_RXCSUM   = 0x05000;
89 const uint32_t REG_RLPML    = 0x05004;
90 const uint32_t REG_RFCTL    = 0x05008;
91 const uint32_t REG_MTA      = 0x05200;
92 const uint32_t REG_RAL      = 0x05400;
93 const uint32_t REG_RAH      = 0x05404;
94 const uint32_t REG_VFTA     = 0x05600;
96 const uint32_t REG_WUC      = 0x05800;
97 const uint32_t REG_WUFC     = 0x05808;
98 const uint32_t REG_WUS      = 0x05810;
99 const uint32_t REG_MANC     = 0x05820;
100 const uint32_t REG_SWSM     = 0x05B50;
101 const uint32_t REG_FWSM     = 0x05B54;
102 const uint32_t REG_SWFWSYNC = 0x05B5C;
104 const uint8_t EEPROM_READ_OPCODE_SPI    = 0x03;
105 const uint8_t EEPROM_RDSR_OPCODE_SPI    = 0x05;
106 const uint8_t EEPROM_SIZE               = 64;
107 const uint16_t EEPROM_CSUM              = 0xBABA;
109 const uint8_t VLAN_FILTER_TABLE_SIZE    = 128;
110 const uint8_t RCV_ADDRESS_TABLE_SIZE    = 24;
111 const uint8_t MULTICAST_TABLE_SIZE      = 128;
112 const uint32_t STATS_REGS_SIZE           = 0x228;
116 const uint8_t PHY_PSTATUS       = 0x1;
117 const uint8_t PHY_PID           = 0x2;
118 const uint8_t PHY_EPID          = 0x3;
119 const uint8_t PHY_GSTATUS       = 10;
120 const uint8_t PHY_EPSTATUS      = 15;
121 const uint8_t PHY_AGC           = 18;
124 const uint16_t RXDS_DYNINT      = 0x800;
125 const uint16_t RXDS_UDPV        = 0x400;
126 const uint16_t RXDS_CRCV        = 0x100;
127 const uint16_t RXDS_PIF         = 0x080;
128 const uint16_t RXDS_IPCS        = 0x040;
129 const uint16_t RXDS_TCPCS       = 0x020;
130 const uint16_t RXDS_UDPCS       = 0x010;
131 const uint16_t RXDS_VP          = 0x008;
132 const uint16_t RXDS_IXSM        = 0x004;
133 const uint16_t RXDS_EOP         = 0x002;
134 const uint16_t RXDS_DD          = 0x001;
137 const uint8_t RXDE_RXE         = 0x80;
138 const uint8_t RXDE_IPE         = 0x40;
139 const uint8_t RXDE_TCPE        = 0x20;
140 const uint8_t RXDE_SEQ         = 0x04;
141 const uint8_t RXDE_SE          = 0x02;
142 const uint8_t RXDE_CE          = 0x01;
145 const uint16_t RXDEE_HBO       = 0x008;
146 const uint16_t RXDEE_CE        = 0x010;
147 const uint16_t RXDEE_LE        = 0x020;
148 const uint16_t RXDEE_PE        = 0x080;
149 const uint16_t RXDEE_OSE       = 0x100;
150 const uint16_t RXDEE_USE       = 0x200;
151 const uint16_t RXDEE_TCPE      = 0x400;
152 const uint16_t RXDEE_IPE       = 0x800;
156 const uint8_t RXDT_LEGACY      = 0x00;
157 const uint8_t RXDT_ADV_ONEBUF  = 0x01;
158 const uint8_t RXDT_ADV_SPLIT_A = 0x05;
161 const uint16_t RXDP_IPV4       = 0x001;
162 const uint16_t RXDP_IPV4E      = 0x002;
163 const uint16_t RXDP_IPV6       = 0x004;
164 const uint16_t RXDP_IPV6E      = 0x008;
165 const uint16_t RXDP_TCP        = 0x010;
166 const uint16_t RXDP_UDP        = 0x020;
167 const uint16_t RXDP_SCTP       = 0x040;
168 const uint16_t RXDP_NFS        = 0x080;
232 const uint8_t TXD_CNXT = 0x0;
233 const uint8_t TXD_DATA = 0x1;
234 const uint8_t TXD_ADVCNXT = 0x2;
235 const uint8_t TXD_ADVDATA = 0x3;
304         const Reg<T> &operator=(T d) { _data = d; return *this;}
308         void serialize(CheckpointOut &cp) const
764     void serialize(CheckpointOut &cp) const override