Lines Matching defs:ADD_FIELD32
291 #define ADD_FIELD32(NAME, OFFSET, BITS) \
320 ADD_FIELD32(fd,0,1); // full duplex
321 ADD_FIELD32(bem,1,1); // big endian mode
322 ADD_FIELD32(pcipr,2,1); // PCI priority
323 ADD_FIELD32(lrst,3,1); // link reset
324 ADD_FIELD32(tme,4,1); // test mode enable
325 ADD_FIELD32(asde,5,1); // Auto-speed detection
326 ADD_FIELD32(slu,6,1); // Set link up
327 ADD_FIELD32(ilos,7,1); // invert los-of-signal
328 ADD_FIELD32(speed,8,2); // speed selection bits
329 ADD_FIELD32(be32,10,1); // big endian mode 32
330 ADD_FIELD32(frcspd,11,1); // force speed
331 ADD_FIELD32(frcdpx,12,1); // force duplex
332 ADD_FIELD32(duden,13,1); // dock/undock enable
333 ADD_FIELD32(dudpol,14,1); // dock/undock polarity
334 ADD_FIELD32(fphyrst,15,1); // force phy reset
335 ADD_FIELD32(extlen,16,1); // external link status enable
336 ADD_FIELD32(rsvd,17,1); // reserved
337 ADD_FIELD32(sdp0d,18,1); // software controlled pin data
338 ADD_FIELD32(sdp1d,19,1); // software controlled pin data
339 ADD_FIELD32(sdp2d,20,1); // software controlled pin data
340 ADD_FIELD32(sdp3d,21,1); // software controlled pin data
341 ADD_FIELD32(sdp0i,22,1); // software controlled pin dir
342 ADD_FIELD32(sdp1i,23,1); // software controlled pin dir
343 ADD_FIELD32(sdp2i,24,1); // software controlled pin dir
344 ADD_FIELD32(sdp3i,25,1); // software controlled pin dir
345 ADD_FIELD32(rst,26,1); // reset
346 ADD_FIELD32(rfce,27,1); // receive flow control enable
347 ADD_FIELD32(tfce,28,1); // transmit flow control enable
348 ADD_FIELD32(rte,29,1); // routing tag enable
349 ADD_FIELD32(vme,30,1); // vlan enable
350 ADD_FIELD32(phyrst,31,1); // phy reset
356 ADD_FIELD32(fd,0,1); // full duplex
357 ADD_FIELD32(lu,1,1); // link up
358 ADD_FIELD32(func,2,2); // function id
359 ADD_FIELD32(txoff,4,1); // transmission paused
360 ADD_FIELD32(tbimode,5,1); // tbi mode
361 ADD_FIELD32(speed,6,2); // link speed
362 ADD_FIELD32(asdv,8,2); // auto speed detection value
363 ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
364 ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot
365 ADD_FIELD32(bus64,12,1); // in 64 bit slot
366 ADD_FIELD32(pcix,13,1); // Pci mode
367 ADD_FIELD32(pcixspd,14,2); // pci x speed
373 ADD_FIELD32(sk,0,1); // clack input to the eeprom
374 ADD_FIELD32(cs,1,1); // chip select to eeprom
375 ADD_FIELD32(din,2,1); // data input to eeprom
376 ADD_FIELD32(dout,3,1); // data output bit
377 ADD_FIELD32(fwe,4,2); // flash write enable
378 ADD_FIELD32(ee_req,6,1); // request eeprom access
379 ADD_FIELD32(ee_gnt,7,1); // grant eeprom access
380 ADD_FIELD32(ee_pres,8,1); // eeprom present
381 ADD_FIELD32(ee_size,9,1); // eeprom size
382 ADD_FIELD32(ee_sz1,10,1); // eeprom size
383 ADD_FIELD32(rsvd,11,2); // reserved
384 ADD_FIELD32(ee_type,13,1); // type of eeprom
390 ADD_FIELD32(start,0,1); // start read
391 ADD_FIELD32(done,1,1); // done read
392 ADD_FIELD32(addr,2,14); // address
393 ADD_FIELD32(data,16,16); // data
399 ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
400 ADD_FIELD32(phyint,5,1); // reads the phy internal int status
401 ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp
402 ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp
403 ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
404 ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
405 ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection
406 ADD_FIELD32(eerst,13,1); // reset the eeprom
407 ADD_FIELD32(spd_byps,15,1); // bypass speed select
408 ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering
409 ADD_FIELD32(vreg,21,1); // power down the voltage regulator
410 ADD_FIELD32(link_mode,22,2); // interface to talk to the link
411 ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ??
412 ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
413 ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
419 ADD_FIELD32(data,0,16); // data
420 ADD_FIELD32(regadd,16,5); // register address
421 ADD_FIELD32(phyadd,21,5); // phy addresses
422 ADD_FIELD32(op,26,2); // opcode
423 ADD_FIELD32(r,28,1); // ready
424 ADD_FIELD32(i,29,1); // interrupt
425 ADD_FIELD32(e,30,1); // error
431 ADD_FIELD32(txdw,0,1) // tx descr witten back
432 ADD_FIELD32(txqe,1,1) // tx queue empty
433 ADD_FIELD32(lsc,2,1) // link status change
434 ADD_FIELD32(rxseq,3,1) // rcv sequence error
435 ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
436 ADD_FIELD32(rsvd1,5,1) // reserved
437 ADD_FIELD32(rxo,6,1) // receive overrunn
438 ADD_FIELD32(rxt0,7,1) // receiver timer interrupt
439 ADD_FIELD32(mdac,9,1) // mdi/o access complete
440 ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets
441 ADD_FIELD32(phyint,12,1) // phy interrupt
442 ADD_FIELD32(gpi1,13,1) // gpi int 1
443 ADD_FIELD32(gpi2,14,1) // gpi int 2
444 ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
445 ADD_FIELD32(srpd,16,1) // small receive packet detected
446 ADD_FIELD32(ack,17,1); // receive ack frame
447 ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
455 ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
467 ADD_FIELD32(rst,0,1); // Reset
468 ADD_FIELD32(en,1,1); // Enable
469 ADD_FIELD32(sbp,2,1); // Store bad packets
470 ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled
471 ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled
472 ADD_FIELD32(lpe,5,1); // long packet reception enabled
473 ADD_FIELD32(lbm,6,2); //
474 ADD_FIELD32(rdmts,8,2); //
475 ADD_FIELD32(mo,12,2); //
476 ADD_FIELD32(mdr,14,1); //
477 ADD_FIELD32(bam,15,1); //
478 ADD_FIELD32(bsize,16,2); //
479 ADD_FIELD32(vfe,18,1); //
480 ADD_FIELD32(cfien,19,1); //
481 ADD_FIELD32(cfi,20,1); //
482 ADD_FIELD32(dpf,22,1); // discard pause frames
483 ADD_FIELD32(pmcf,23,1); // pass mac control frames
484 ADD_FIELD32(bsex,25,1); // buffer size extension
485 ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
502 ADD_FIELD32(ttv,0,16); // Transmit Timer Value
508 ADD_FIELD32(rst,0,1); // Reset
509 ADD_FIELD32(en,1,1); // Enable
510 ADD_FIELD32(bce,2,1); // busy check enable
511 ADD_FIELD32(psp,3,1); // pad short packets
512 ADD_FIELD32(ct,4,8); // collision threshold
513 ADD_FIELD32(cold,12,10); // collision distance
514 ADD_FIELD32(swxoff,22,1); // software xoff transmission
515 ADD_FIELD32(pbe,23,1); // packet burst enable
516 ADD_FIELD32(rtlc,24,1); // retransmit late collisions
517 ADD_FIELD32(nrtu,25,1); // on underrun no TX
518 ADD_FIELD32(mulr,26,1); // multiple request
524 ADD_FIELD32(rxa,0,16);
525 ADD_FIELD32(txa,16,16);
531 ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
533 ADD_FIELD32(xone, 31,1);
539 ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
541 ADD_FIELD32(xfce, 31,1);
554 ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
560 ADD_FIELD32(pktlen, 0, 8);
561 ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
562 ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv,
571 ADD_FIELD32(rdh,0,16); // head of the descriptor ring
577 ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
583 ADD_FIELD32(delay,0,16); // receive delay timer
584 ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
590 ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
592 ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to
594 ADD_FIELD32(wthresh,16,6); // writeback threshold
595 ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline
601 ADD_FIELD32(idv,0,16); // absolute interrupt delay
607 ADD_FIELD32(idv,0,12); // size to interrutp on small packets
620 ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
626 ADD_FIELD32(tdh,0,16); // head of the descriptor ring
632 ADD_FIELD32(cpu_mask, 0, 5);
633 ADD_FIELD32(enabled, 5,1);
634 ADD_FIELD32(relax_ordering, 6, 1);
640 ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
646 ADD_FIELD32(idv,0,16); // interrupt delay
652 ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
654 ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory
656 ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until
658 ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline,
660 ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
667 ADD_FIELD32(idv,0,16); // absolute interrupt delay
682 ADD_FIELD32(pcss,0,8);
683 ADD_FIELD32(ipofld,8,1);
684 ADD_FIELD32(tuofld,9,1);
685 ADD_FIELD32(pcsd, 13,1);
693 ADD_FIELD32(iscsi_dis,0,1);
694 ADD_FIELD32(iscsi_dwc,1,5);
695 ADD_FIELD32(nfsw_dis,6,1);
696 ADD_FIELD32(nfsr_dis,7,1);
697 ADD_FIELD32(nfs_ver,8,2);
698 ADD_FIELD32(ipv6_dis,10,1);
699 ADD_FIELD32(ipv6xsum_dis,11,1);
700 ADD_FIELD32(ackdis,13,1);
701 ADD_FIELD32(ipfrsp_dis,14,1);
702 ADD_FIELD32(exsten,15,1);
708 ADD_FIELD32(smbus,0,1); // SMBus enabled #####
709 ADD_FIELD32(asf,1,1); // ASF enabled #####
710 ADD_FIELD32(ronforce,2,1); // reset of force
711 ADD_FIELD32(rsvd,3,5); // reserved
712 ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering
713 ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering
714 ADD_FIELD32(ipv4,10,1); // enable ipv4
715 ADD_FIELD32(ipv6,11,1); // enable ipv6
716 ADD_FIELD32(snap,12,1); // accept snap
717 ADD_FIELD32(arp,13,1); // filter arp #####
718 ADD_FIELD32(neighbor,14,1); // neighbor discovery
719 ADD_FIELD32(arp_resp,15,1); // arp response
720 ADD_FIELD32(tcorst,16,1); // tco reset happened
721 ADD_FIELD32(rcvtco,17,1); // receive tco enabled ######
722 ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
723 ADD_FIELD32(rcvall,19,1); // receive all
724 ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
725 ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
726 ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
727 ADD_FIELD32(xsumfilter,23,1); // checksum filtering
728 ADD_FIELD32(brfilter,24,1); // broadcast filtering
729 ADD_FIELD32(smbreq,25,1); // smb request
730 ADD_FIELD32(smbgnt,26,1); // smb grant
731 ADD_FIELD32(smbclkin,27,1); // smbclkin
732 ADD_FIELD32(smbdatain,28,1); // smbdatain
733 ADD_FIELD32(smbdataout,29,1); // smb data out
734 ADD_FIELD32(smbclkout,30,1); // smb clock out
740 ADD_FIELD32(smbi,0,1); // Semaphone bit
741 ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore
742 ADD_FIELD32(wmng, 2,1); // Wake MNG clock
743 ADD_FIELD32(reserved, 3, 29);
749 ADD_FIELD32(eep_fw_semaphore,0,1);
750 ADD_FIELD32(fw_mode, 1,3);
751 ADD_FIELD32(ide, 4,1);
752 ADD_FIELD32(sol, 5,1);
753 ADD_FIELD32(eep_roload, 6,1);
754 ADD_FIELD32(reserved, 7,8);
755 ADD_FIELD32(fw_val_bit, 15, 1);
756 ADD_FIELD32(reset_cnt, 16, 3);
757 ADD_FIELD32(ext_err_ind, 19, 6);
758 ADD_FIELD32(reserved2, 25, 7);