dev/net/i8254xGBe.cc

826     : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0),
896             igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT);
898             igbe->anWe(annSmWb, annUsedCacheQ);
905     igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
906     igbe->anBegin(annSmWb, "Prepare Writeback Desc");
914     if (igbe->drainState() != DrainState::Running) {
915         igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
924         igbe->anPq(annSmWb, annUsedCacheQ);
925         igbe->anPq(annSmWb, annDescQ);
926         igbe->anQ(annSmWb, annUsedDescQ);
930     igbe->anBegin(annSmWb, "Writeback Desc DMA");
933     igbe->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T)),
935                    igbe->wbCompDelay);
959         igbe->anWe(annSmFetch, annUnusedDescQ);
961         igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch);
965             igbe->anWf(annSmFetch, annDescQ);
967             igbe->anRq(annSmFetch, annDescQ, free_cache);
986     igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
987     igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
995     if (igbe->drainState() != DrainState::Running) {
996         igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
1000     igbe->anBegin(annSmFetch, "Fetch Desc");
1007     igbe->dmaRead(pciToDma(descBase() + cachePnt * sizeof(T)),
1009                   igbe->fetchCompDelay);
1017     igbe->anBegin(annSmFetch, "Fetch Complete");
1022         igbe->anDq(annSmFetch, annUnusedDescQ);
1023         igbe->anQ(annSmFetch, annUnusedCacheQ);
1024         igbe->anQ(annSmFetch, annDescQ);
1045         igbe->anWe(annSmFetch, annUnusedDescQ);
1047         igbe->anWf(annSmFetch, annDescQ);
1049         igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT);
1053     igbe->checkDrain();
1061     igbe->anBegin(annSmWb, "Finish Writeback");
1073         igbe->anDq(annSmWb, annUsedCacheQ);
1074         igbe->anDq(annSmWb, annDescQ);
1098         igbe->checkDrain();
1100             igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT);
1102             igbe->anWe(annSmWb, annUsedCacheQ);
1191         igbe->schedule(fetchDelayEvent, fetch_delay);
1193         igbe->schedule(wbDelayEvent, wb_delay);
1243     switch (igbe->regs.srrctl.desctype()) {
1248                 packet->length, igbe->regs.rctl.descSize());
1249         assert(packet->length < igbe->regs.rctl.descSize());
1250         igbe->dmaWrite(pciToDma(desc->legacy.buf),
1252                        igbe->rxWriteDelay);
1257         buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1258             igbe->regs.rctl.descSize();
1260                 packet->length, igbe->regs.srrctl(), buf_len);
1262         igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1264                        igbe->rxWriteDelay);
1272         buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1273             igbe->regs.rctl.descSize();
1274         hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0;
1278                 igbe->regs.rctl.lpe(), packet->length, pkt_offset,
1279                 igbe->regs.srrctl(), desc->adv_read.hdr, hdr_len,
1288             igbe->dmaWrite(pciToDma(desc->adv_read.hdr),
1290                            igbe->rxWriteDelay);
1303                 igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1305                                packet->data + pkt_offset, igbe->rxWriteDelay);
1316                 igbe->dmaWrite(pciToDma(desc->adv_read.hdr),
1318                                packet->data, igbe->rxWriteDelay);
1319                 igbe->dmaWrite(pciToDma(desc->adv_read.pkt),
1321                                packet->data + split_point, igbe->rxWriteDelay);
1333               igbe->regs.srrctl.desctype());
1346     igbe->anBegin("RXS", "Update Desc");
1348     uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
1356     assert(igbe->regs.rxcsum.pcss() == 0);
1384         if (ip && igbe->regs.rxcsum.ipofld()) {
1388             igbe->rxIpChecksums++;
1396         if (tcp && igbe->regs.rxcsum.tuofld()) {
1401             igbe->rxTcpChecksums++;
1410         if (udp && igbe->regs.rxcsum.tuofld()) {
1415             igbe->rxUdpChecksums++;
1426     switch (igbe->regs.srrctl.desctype()) {
1438         if (igbe->regs.rxcsum.pcsd()) {
1452               igbe->regs.srrctl.desctype());
1462         if (igbe->regs.rdtr.delay()) {
1463             Tick delay = igbe->regs.rdtr.delay() * igbe->intClock();
1465             igbe->reschedule(igbe->rdtrEvent, curTick() + delay);
1468         if (igbe->regs.radv.idv()) {
1469             Tick delay = igbe->regs.radv.idv() * igbe->intClock();
1471             if (!igbe->radvEvent.scheduled()) {
1472                 igbe->schedule(igbe->radvEvent, curTick() + delay);
1477         if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
1480             igbe->postInterrupt(IT_RXT);
1485         if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
1488             igbe->postInterrupt(IT_SRPD);
1494     igbe->checkDrain();
1498     igbe->anBegin("RXS", "Done Updating Desc");
1500     igbe->anDq("RXS", annUnusedCacheQ);
1502     igbe->anQ("RXS", annUsedCacheQ);
1509     if (igbe->drainState() != DrainState::Draining) {
1510         igbe->rxTick = true;
1511         igbe->restartClock();
1617         igbe->anDq("TXS", annUnusedCacheQ);
1619         igbe->anQ("TXS", annUsedCacheQ);
1647         igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
1674     igbe->checkDrain();
1752         igbe->dmaRead(pciToDma(TxdOp::getBuf(desc))
1755                       igbe->txReadDelay);
1759         igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
1761                       igbe->txReadDelay);
1773     igbe->anBegin("TXS", "Update Desc");
1806         igbe->anDq("TXS", annUnusedCacheQ);
1808         igbe->anQ("TXS", annUsedCacheQ);
1821         igbe->checkDrain();
1887             igbe->txIpChecksums++;
1896                 igbe->txTcpChecksums++;
1902                 igbe->txUdpChecksums++;
1913         if (igbe->regs.tidv.idv()) {
1914             Tick delay = igbe->regs.tidv.idv() * igbe->intClock();
1916             igbe->reschedule(igbe->tidvEvent, curTick() + delay, true);
1919         if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
1920             Tick delay = igbe->regs.tadv.idv() * igbe->intClock();
1922             if (!igbe->tadvEvent.scheduled()) {
1923                 igbe->schedule(igbe->tadvEvent, curTick() + delay);
1931         igbe->anDq("TXS", annUnusedCacheQ);
1933         igbe->anQ("TXS", annUsedCacheQ);
1950     if (igbe->regs.txdctl.wthresh() == 0) {
1951         igbe->anBegin("TXS", "Desc Writeback");
1954     } else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <=
1957         igbe->anBegin("TXS", "Desc Writeback");
1958         writeback((igbe->cacheBlockSize()-1)>>4);
1959     } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) {
1961         igbe->anBegin("TXS", "Desc Writeback");
1962         writeback((igbe->cacheBlockSize()-1)>>4);
1966     igbe->checkDrain();
1974     igbe->postInterrupt(iGbReg::IT_TXDW);
1976         descEnd = igbe->regs.tdh();
1980         igbe->dmaWrite(pciToDma(mbits(completionAddress, 63, 2)),
2056     if (igbe->drainState() != DrainState::Draining) {
2057         igbe->txTick = true;
2058         igbe->restartClock();