dev/net/i8254xGBe.cc

896             igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT);
906     igbe->anBegin(annSmWb, "Prepare Writeback Desc");
930     igbe->anBegin(annSmWb, "Writeback Desc DMA");
987     igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
1000     igbe->anBegin(annSmFetch, "Fetch Desc");
1017     igbe->anBegin(annSmFetch, "Fetch Complete");
1049         igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT);
1061     igbe->anBegin(annSmWb, "Finish Writeback");
1100             igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT);
1346     igbe->anBegin("RXS", "Update Desc");
1498     igbe->anBegin("RXS", "Done Updating Desc");
1773     igbe->anBegin("TXS", "Update Desc");
1951         igbe->anBegin("TXS", "Desc Writeback");
1957         igbe->anBegin("TXS", "Desc Writeback");
1961         igbe->anBegin("TXS", "Desc Writeback");
2155         anBegin("TXS", "Desc Writeback");
2174             anBegin("TXS", "Desc Writeback");
2176             anBegin("TXS", "Desc Fetch");
2187             anBegin("TXS", "Desc Fetch");
2209             anBegin("TXS", "DMA Packet");
2218             anBegin("TXS", "Desc Writeback");
2241     anBegin("RXQ", "Wire Recv");
2246         anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
2261         anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
2311             anBegin("RXS", "Writeback Descriptors");
2324             anBegin("RXS", "Writeback Descriptors");
2336             anBegin("RXS", "Fetch Descriptors");
2341             anBegin("RXS", "Fetch Descriptors");
2359         anBegin("RXS", "Fetch Descriptors");
2377     anBegin("RXS", "Get Desc");
2386         anBegin( "RXS", "FIFO Dequeue");
2396     anBegin("RXS", "DMA Packet");
2422         anBegin("TXQ", "Wire Send");
2465     anBegin("TXQ", "Send Done");