dev/arm/ufs_device.cc

1310             transactionStart[count] = curTick(); //note the start time
1317              * step3 start transfer
1330             DPRINTF(UFSHostDevice, "Initial transfer start: 0x%8x\n",
1346  * Task start event
1352     DPRINTF(UFSHostDevice, "Task start");
1360  * Transfer start event
1630             DPRINTF(UFSHostDevice, "Data DMA start: 0x%8x\n", SCSI_start);
1716     DPRINTF(UFSHostDevice, "DMA start: 0x%8x; DMA size: 0x%8x\n",
1730     DPRINTF(UFSHostDevice, "Transfer done start\n");
1793     DPRINTF(UFSHostDevice, "Read done start\n");
1881                            start, int size, uint8_t* destination, uint64_t
1885             start, size);
1912         dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1920         dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1947         next_packet.start = sglist[count].upperAddr;
1948         next_packet.start = (next_packet.start << 32) |
1951         DPRINTF(UFSHostDevice, "Write data DMA start: 0x%8x\n",
1952                 next_packet.start);
1965             writeDevice(NULL, true, next_packet.start, next_packet.size,
1999     /**If there is nothing on the way, we need to start the events*/
2026         writeDevice(NULL, true, dmaWriteInfo.front().start,
2034  * SSD write start. Starts the write action in the timing model
2086 UFSHostDevice::readDevice(bool lastTransfer, Addr start, uint32_t size,
2090     DPRINTF(UFSHostDevice, "Read start: 0x%8x; Size: %d, data[0]: 0x%8x\n",
2091             start, size, (reinterpret_cast<uint32_t *>(destination))[0]);
2100         dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2108         dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2142         DPRINTF(UFSHostDevice, "Data READ start: 0x%8x; size: %d\n",
2180  * SSDisk start read; this function was created to keep the interfaces