Lines Matching defs:write
60 * transaction flow, data write transfer and data read transfer. The
153 * Synchronize Cache and buffer read/write could not be tested yet
709 /** Get from fifo and write to image*/
711 flashDisk->write(&(writeaddr[SectorSize * count]),
795 .desc("Most up to date length of the write SSD queue")
836 .desc("Average write bandwidth (bytes/s)")
851 .desc("Average write queue length")
1062 * UFSHCD write function. This function allows access to the writeable
1063 * registers. If any function attempts to write value to an unwriteable
1067 UFSHostDevice::write(PacketPtr pkt)
1086 panic("Undefined UFSHCD controller write size!\n");
1092 case regControllerCapabilities://you shall not write to this
1095 case regUFSVersion://you shall not write to this
1098 case regControllerDEVID://you shall not write to this
1101 case regControllerPRODID://you shall not write to this
1104 case regInterruptStatus://you shall not write to this
1607 /**write transfer*/
1864 * they pass through their queues. For a write action the stages are ordered
1874 * Dma transaction function: write device. Note that the dma action is
1915 //yes, a readreq at a write device function is correct.
1927 * Manage write transfer. Manages correct transfer flow and makes sure that
2034 * SSD write start. Starts the write action in the timing model
2052 * SSDisk write done