dev/arm/ufs_device.cc

57  * needs to manage the data transfer. This file is build up as follows: first
60  * transaction flow, data write transfer and data read transfer. The
113     lunInfo.dWord0 = 0x02060000;   //data
684     sensecodelist[8] = 0x1F; //data length
798     /** Amount of data read/written */
931     uint32_t data = 0;
937         data = UFSHCIMem.HCCAP;
941         data = UFSHCIMem.HCversion;
945         data = UFSHCIMem.HCHCDDID;
949         data = UFSHCIMem.HCHCPMID;
953         data = UFSHCIMem.ORInterruptStatus;
960         data = UFSHCIMem.ORInterruptEnable;
964         data = UFSHCIMem.ORHostControllerStatus;
968         data = UFSHCIMem.ORHostControllerEnable;
972         data = UFSHCIMem.ORUECPA;
976         data = UFSHCIMem.ORUECDL;
980         data = UFSHCIMem.ORUECN;
984         data = UFSHCIMem.ORUECT;
988         data = UFSHCIMem.ORUECDME;
992         data = UFSHCIMem.ORUTRIACR;
996         data = UFSHCIMem.TRUTRLBA;
1000         data = UFSHCIMem.TRUTRLBAU;
1004         data = UFSHCIMem.TRUTRLDBR;
1008         data = UFSHCIMem.TRUTRLCLR;
1012         data = UFSHCIMem.TRUTRLRSR;
1016         data = UFSHCIMem.TMUTMRLBA;
1020         data = UFSHCIMem.TMUTMRLBAU;
1024         data = UFSHCIMem.TMUTMRLDBR;
1028         data = UFSHCIMem.TMUTMRLCLR;
1032         data = UFSHCIMem.TMUTMRLRSR;
1036         data = UFSHCIMem.CMDUICCMDR;
1040         data = UFSHCIMem.CMDUCMDARG1;
1044         data = UFSHCIMem.CMDUCMDARG2;
1048         data = UFSHCIMem.CMDUCMDARG3;
1052         data = 0x00;
1056     pkt->setLE<uint32_t>(data);
1069     uint32_t data = 0;
1074         data = pkt->getLE<uint8_t>();
1078         data = pkt->getLE<uint16_t>();
1082         data = pkt->getLE<uint32_t>();
1108         UFSHCIMem.ORInterruptEnable = data;
1112         UFSHCIMem.ORHostControllerStatus = data;
1116         UFSHCIMem.ORHostControllerEnable = data;
1120         UFSHCIMem.ORUECPA = data;
1124         UFSHCIMem.ORUECDL = data;
1128         UFSHCIMem.ORUECN = data;
1132         UFSHCIMem.ORUECT = data;
1136         UFSHCIMem.ORUECDME = data;
1140         UFSHCIMem.ORUTRIACR = data;
1144         UFSHCIMem.TRUTRLBA = data;
1151         UFSHCIMem.TRUTRLBAU = data;
1158         if (!(UFSHCIMem.TRUTRLDBR) && data)
1160         UFSHCIMem.TRUTRLDBR |= data;
1165         UFSHCIMem.TRUTRLCLR = data;
1169         UFSHCIMem.TRUTRLRSR = data;
1173         UFSHCIMem.TMUTMRLBA = data;
1180         UFSHCIMem.TMUTMRLBAU = data;
1187         UFSHCIMem.TMUTMRLDBR |= data;
1192         UFSHCIMem.TMUTMRLCLR = data;
1196         UFSHCIMem.TMUTMRLRSR = data;
1200         UFSHCIMem.CMDUICCMDR = data;
1205         UFSHCIMem.CMDUCMDARG1 = data;
1209         UFSHCIMem.CMDUCMDARG2 = data;
1213         UFSHCIMem.CMDUCMDARG3 = data;
1501          * loading next data packet in case Another LUN
1516  * apart from the data transfer, this also generates its own reply (UPIU
1565     /**amount of data that will follow*/
1569     //data
1602      * In this part the data that needs to be transfered will be initiated
1623         /**Transport the SCSI reponse data according to the SG list*/
1635              * the amount of data allocated, which can potentially lead to
1636              * some garbage data being send over. Hence this construction
1637              * that finds the least amount of data that needs to be
1701  * Transfer done. When the data transfer is done, this function ensures
1859  * buffer, or a buffer that is big enough to store all the data in the
1951         DPRINTF(UFSHostDevice, "Write data DMA start: 0x%8x\n",
1953         DPRINTF(UFSHostDevice, "Write data DMA size: 0x%8x\n",
2090     DPRINTF(UFSHostDevice, "Read start: 0x%8x; Size: %d, data[0]: 0x%8x\n",
2232     /**Callback; make sure data is transfered upstream:
2288     DPRINTF(UFSHostDevice, "Clean read data, %d\n", SSDReadPending.size());