dev/arm/smmu_v3_transl.cc

169     TranslResult tr;
176         if (hazard4kCheck() || ifcTLBLookup(yield, tr, wasPrefetched))
181         tr = smmuTranslation(yield);
183         if (tr.fault == FAULT_NONE)
184             ifcTLBUpdate(yield, tr);
192         if (!microTLBLookup(yield, tr)) {
193             bool hit = ifcTLBLookup(yield, tr, wasPrefetched);
197                     hit = ifcTLBLookup(yield, tr, wasPrefetched);
210                 tr = smmuTranslation(yield);
212                 if (tr.fault == FAULT_NONE) {
213                     ifcTLBUpdate(yield, tr);
221             if (tr.fault == FAULT_NONE)
222                 microTLBUpdate(yield, tr);
228         if (tr.fault != FAULT_NONE)
231         completeTransaction(yield, tr);
238     TranslResult tr;
239     tr.fault = FAULT_NONE;
240     tr.addr = addr;
241     tr.addrMask = 0;
242     tr.writable = 1;
244     return tr;
250     TranslResult tr;
263         if(findConfig(yield, context, tr)) {
270     if (haveConfig && !smmuTLBLookup(yield, tr)) {
280             tr = translateStage1And2(yield, request.addr);
282             tr = translateStage2(yield, request.addr, true);
284             tr = bypass(request.addr);
293         if (tr.fault == FAULT_NONE)
294             smmuTLBUpdate(yield, tr);
306     return tr;
310 SMMUTranslationProcess::microTLBLookup(Yield &yield, TranslResult &tr)
332     tr.fault = FAULT_NONE;
333     tr.addr = e->pa + (request.addr & ~e->vaMask);;
334     tr.addrMask = e->vaMask;
335     tr.writable = e->permissions;
341 SMMUTranslationProcess::ifcTLBLookup(Yield &yield, TranslResult &tr,
366     tr.fault = FAULT_NONE;
367     tr.addr = e->pa + (request.addr & ~e->vaMask);;
368     tr.addrMask = e->vaMask;
369     tr.writable = e->permissions;
376 SMMUTranslationProcess::smmuTLBLookup(Yield &yield, TranslResult &tr)
398     tr.fault = FAULT_NONE;
399     tr.addr = e->pa + (request.addr & ~e->vaMask);;
400     tr.addrMask = e->vaMask;
401     tr.writable = e->permissions;
408                                        const TranslResult &tr)
410     assert(tr.fault == FAULT_NONE);
420     e.vaMask = tr.addrMask;
422     e.pa = tr.addr & e.vaMask;
423     e.permissions = tr.writable;
440                                      const TranslResult &tr)
442     assert(tr.fault == FAULT_NONE);
452     e.vaMask = tr.addrMask;
454     e.pa = tr.addr & e.vaMask;
455     e.permissions = tr.writable;
477                                       const TranslResult &tr)
479     assert(tr.fault == FAULT_NONE);
486     e.vaMask = tr.addrMask;
490     e.pa = tr.addr & e.vaMask;
491     e.permissions = tr.writable;
579                                    TranslResult &tr)
760             TranslResult tr;
761             tr.fault = FAULT_TRANSLATION;
762             return tr;
770             TranslResult tr;
771             tr.fault = FAULT_PERMISSION;
772             return tr;
792     TranslResult tr;
793     tr.fault    = FAULT_NONE;
794     tr.addrMask = pt_ops->pageMask(pte, level);
795     tr.addr     = walkPtr + (addr & ~tr.addrMask);
796     tr.writable = pt_ops->isWritable(pte, level, false);
799         TranslResult s2tr = translateStage2(yield, tr.addr, true);
803         tr = combineTranslations(tr, s2tr);
806     walkCacheUpdate(yield, addr, tr.addrMask, tr.addr,
807                     1, level, true, tr.writable);
809     return tr;
844             TranslResult tr;
845             tr.fault = FAULT_TRANSLATION;
846             return tr;
854             TranslResult tr;
855             tr.fault = FAULT_PERMISSION;
856             return tr;
869     TranslResult tr;
870     tr.fault    = FAULT_NONE;
871     tr.addrMask = pt_ops->pageMask(pte, level);
872     tr.addr     = walkPtr + (addr & ~tr.addrMask);
873     tr.writable = pt_ops->isWritable(pte, level, true);
875     return tr;
903     TranslResult tr;
906             tr.fault    = FAULT_NONE;
907             tr.addr     = walk_ep->pa + (addr & ~walk_ep->vaMask);
908             tr.addrMask = walk_ep->vaMask;
909             tr.writable = walk_ep->permissions;
911             tr = walkStage1And2(yield, addr, pt_ops, level+1, walk_ep->pa);
923         tr = walkStage1And2(yield, addr, pt_ops,
928     if (tr.fault == FAULT_NONE)
929         DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
931     return tr;
949         TranslResult tr;
950         tr.fault    = FAULT_NONE;
951         tr.addr     = ipa_ep->pa + (addr & ~ipa_ep->ipaMask);
952         tr.addrMask = ipa_ep->ipaMask;
953         tr.writable = ipa_ep->permissions;
956             addr, context.vmid, tr.addr);
958         return tr;
985     TranslResult tr;
988             tr.fault    = FAULT_NONE;
989             tr.addr     = walk_ep->pa + (addr & ~walk_ep->vaMask);
990             tr.addrMask = walk_ep->vaMask;
991             tr.writable = walk_ep->permissions;
993             tr = walkStage2(yield, addr, final_tr, pt_ops,
997         tr = walkStage2(yield, addr, final_tr, pt_ops,
1002     if (tr.fault == FAULT_NONE)
1004             context.stage1Enable ? "ip" : "v", addr, tr.addr);
1009         e.ipaMask = tr.addrMask;
1011         e.pa = tr.addr & tr.addrMask;
1012         e.permissions = tr.writable;
1020     return tr;
1032     TranslResult tr;
1033     tr.fault    = FAULT_NONE;
1034     tr.addr     = s2tr.addr;
1035     tr.addrMask = s1tr.addrMask | s2tr.addrMask;
1036     tr.writable = s1tr.writable & s2tr.writable;
1038     return tr;
1224                                             const TranslResult &tr)
1226     assert(tr.fault == FAULT_NONE);
1267     a.pkt->setAddr(tr.addr);
1268     a.pkt->req->setPaddr(tr.addr);