dev/arm/smmu_v3_transl.cc

119     assert(smmu.system.isTimingMode());
131     smmu.runProcessTiming(this, request.pkt);
162     if (!(smmu.regs.cr0 & CR0_SMMUEN_MASK)) {
253     doSemaphoreDown(yield, smmu.transSem);
256     doSemaphoreDown(yield, smmu.ifcSmmuSem);
258     doSemaphoreUp(smmu.ifcSmmuSem);
259     doDelay(yield, smmu.ifcSmmuLat - Cycles(1)); // remaining pipeline delay
274         doSemaphoreDown(yield, smmu.ptwSem);
288             smmu.ptwTimeDist.sample(curTick() - ptwStartTick);
291         doSemaphoreUp(smmu.ptwSem);
298     doSemaphoreDown(yield, smmu.smmuIfcSem);
300     doSemaphoreUp(smmu.smmuIfcSem);
301     doDelay(yield, smmu.smmuIfcLat - Cycles(1)); // remaining pipeline delay
304     doSemaphoreUp(smmu.transSem);
378     if (!smmu.tlbEnable)
381     doSemaphoreDown(yield, smmu.tlbSem);
382     doDelay(yield, smmu.tlbLat);
384         smmu.tlb.lookup(request.addr, context.asid, context.vmid);
385     doSemaphoreUp(smmu.tlbSem);
481     if (!smmu.tlbEnable)
493     doSemaphoreDown(yield, smmu.tlbSem);
499     smmu.tlb.store(e);
501     doSemaphoreUp(smmu.tlbSem);
507     if (!smmu.configCacheEnable)
510     doSemaphoreDown(yield, smmu.configSem);
511     doDelay(yield, smmu.configLat);
513         smmu.configCache.lookup(request.sid, request.ssid);
514     doSemaphoreUp(smmu.configSem);
548     if (!smmu.configCacheEnable)
567     doSemaphoreDown(yield, smmu.configSem);
571     smmu.configCache.store(e);
573     doSemaphoreUp(smmu.configSem);
658             smmu.getPageTableOps(context.stage1TranslGranule) :
659             smmu.getPageTableOps(context.stage2TranslGranule);
662         smmu.walkCacheEnable ?
663             (stage == 1 ? smmu.walkCacheS1Levels : smmu.walkCacheS2Levels) :
667         doSemaphoreDown(yield, smmu.walkSem);
668         doDelay(yield, smmu.walkLat);
670         walkEntry = smmu.walkCache.lookup(addr, pt_ops->walkMask(level),
683         doSemaphoreUp(smmu.walkSem);
694         stage == 1 ? smmu.walkCacheS1Levels : smmu.walkCacheS2Levels;
696     if (smmu.walkCacheEnable && ((1<<level) & walkCacheLevels)) {
709         doSemaphoreDown(yield, smmu.walkSem);
717         smmu.walkCache.store(e);
719         doSemaphoreUp(smmu.walkSem);
735     doSemaphoreDown(yield, smmu.cycleSem);
737     doSemaphoreUp(smmu.cycleSem);
750         doSemaphoreDown(yield, smmu.cycleSem);
752         doSemaphoreUp(smmu.cycleSem);
819     doSemaphoreDown(yield, smmu.cycleSem);
821     doSemaphoreUp(smmu.cycleSem);
834         doSemaphoreDown(yield, smmu.cycleSem);
836         doSemaphoreUp(smmu.cycleSem);
861         if (final_tr || smmu.walkCacheNonfinalEnable)
882         smmu.getPageTableOps(context.stage1TranslGranule);
938             smmu.getPageTableOps(context.stage2TranslGranule);
941     if (smmu.ipaCacheEnable) {
942         doSemaphoreDown(yield, smmu.ipaSem);
943         doDelay(yield, smmu.ipaLat);
944         ipa_ep = smmu.ipaCache.lookup(addr, context.vmid);
945         doSemaphoreUp(smmu.ipaSem);
959     } else if (smmu.ipaCacheEnable) {
967     if (final_tr || smmu.walkCacheNonfinalEnable) {
1006     if (smmu.ipaCacheEnable) {
1015         doSemaphoreDown(yield, smmu.ipaSem);
1016         smmu.ipaCache.store(e);
1017         doSemaphoreUp(smmu.ipaSem);
1207     if (!smmu.system.isTimingMode())
1215         new SMMUTranslationProcess(proc_name, smmu, ifc);
1219     proc->scheduleWakeup(smmu.clockEdge(Cycles(1)));
1229         (request.size + (smmu.masterPortWidth-1))
1230             / smmu.masterPortWidth :
1233     doSemaphoreDown(yield, smmu.masterPortSem);
1235     doSemaphoreUp(smmu.masterPortSem);
1238     smmu.translationTimeDist.sample(curTick() - recvTick);
1244     smmu.scheduleSlaveRetries();
1252         if (smmu.system.isAtomicMode()) {
1254         } else if (smmu.system.isTimingMode()) {
1300     int sizeMask = mask(smmu.regs.eventq_base & Q_BASE_SIZE_MASK);
1302     if (((smmu.regs.eventq_prod+1) & sizeMask) ==
1303             (smmu.regs.eventq_cons & sizeMask))
1307         (smmu.regs.eventq_base & Q_BASE_ADDR_MASK) +
1308         (smmu.regs.eventq_prod & sizeMask) * sizeof(ev);
1312         event_addr, smmu.regs.eventq_prod, ev.type, ev.stag,
1316     smmu.regs.eventq_prod = (smmu.regs.eventq_prod + 1) & sizeMask;
1320     if (!(smmu.regs.eventq_irq_cfg0 & E_BASE_ENABLE_MASK))
1323     doWrite(yield, smmu.regs.eventq_irq_cfg0 & E_BASE_ADDR_MASK,
1324             &smmu.regs.eventq_irq_cfg1, sizeof(smmu.regs.eventq_irq_cfg1));
1332     unsigned max_sid = 1 << (smmu.regs.strtab_base_cfg & ST_CFG_SIZE_MASK);
1338     if ((smmu.regs.strtab_base_cfg & ST_CFG_FMT_MASK) == ST_CFG_FMT_2LEVEL) {
1340             (smmu.regs.strtab_base_cfg & ST_CFG_SPLIT_MASK) >> ST_CFG_SPLIT_SHIFT;
1347             (smmu.regs.strtab_base & VMT_BASE_ADDR_MASK) +
1367         smmu.steL1Fetches++;
1368     } else if ((smmu.regs.strtab_base_cfg & ST_CFG_FMT_MASK) == ST_CFG_FMT_LINEAR) {
1370             (smmu.regs.strtab_base & VMT_BASE_ADDR_MASK) + sid * sizeof(ste);
1391     smmu.steFetches++;
1429             smmu.cdL1Fetches++;
1455     smmu.cdFetches++;