Lines Matching defs:asid
384 smmu.tlb.lookup(request.addr, context.asid, context.vmid);
388 DPRINTF(SMMUv3, "SMMU TLB miss vaddr=%#x asid=%#x vmid=%#x\n",
389 request.addr, context.asid, context.vmid);
395 "SMMU TLB hit vaddr=%#x amask=%#x asid=%#x vmid=%#x paddr=%#x\n",
396 request.addr, e->vaMask, context.asid, context.vmid, e->pa);
424 e.asid = context.asid;
456 e.asid = context.asid;
488 e.asid = context.asid;
496 "SMMU TLB upd vaddr=%#x amask=%#x paddr=%#x asid=%#x vmid=%#x\n",
497 e.va, e.vaMask, e.pa, e.asid, e.vmid);
523 DPRINTF(SMMUv3, "Config hit sid=%#x ssid=%#x ttb=%#08x asid=%#x\n",
524 request.sid, request.ssid, e->ttb0, e->asid);
531 tc.asid = e->asid;
559 e.asid = tc.asid;
632 tc.asid = cd.dw0.asid;
638 tc.asid = 0;
650 Addr addr, uint16_t asid, uint16_t vmid,
671 asid, vmid, stage, level);
674 DPRINTF(SMMUv3, "%sWalkCache hit va=%#x asid=%#x vmid=%#x "
676 indent, addr, asid, vmid, walkEntry->pa, stage, level);
678 DPRINTF(SMMUv3, "%sWalkCache miss va=%#x asid=%#x vmid=%#x "
680 indent, addr, asid, vmid, stage, level);
701 e.asid = stage==1 ? context.asid : 0;
711 DPRINTF(SMMUv3, "%sWalkCache upd va=%#x mask=%#x asid=%#x vmid=%#x "
714 e.va, e.vaMask, e.asid, e.vmid,
894 context.asid, context.vmid, 1, level-1);