dev/arm/gic_v3_distributor.cc

154         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
155              i++, int_id++) {
156             val |= irqGroup[int_id] << i;
169         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
170              i++, int_id++) {
172             if (nsAccessToSecInt(int_id, is_secure_access))
177             val |= irqEnabled[int_id] << i;
190         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
191              i++, int_id++) {
193             if (nsAccessToSecInt(int_id, is_secure_access))
198             val |= (irqEnabled[int_id] << i);
211         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
212              i++, int_id++) {
214             if (nsAccessToSecInt(int_id, is_secure_access))
216                 if (irqNsacr[int_id] == 0) {
222             val |= (irqPending[int_id] << i);
235         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
236              i++, int_id++) {
238             if (nsAccessToSecInt(int_id, is_secure_access))
240                 if (irqNsacr[int_id] < 2) {
246             val |= (irqPending[int_id] << i);
260         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
261              i++, int_id++) {
263             if (nsAccessToSecInt(int_id, is_secure_access))
266                 if (irqNsacr[int_id] < 2) {
271             val |= (irqActive[int_id] << i);
285         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
286              i++, int_id++) {
288             if (nsAccessToSecInt(int_id, is_secure_access))
290                 if (irqNsacr[int_id] < 2) {
295             val |= (irqActive[int_id] << i);
308         for (int i = 0, int_id = first_intid; i < size && int_id < itLines;
309              i++, int_id++) {
311             uint8_t prio = irqPriority[int_id];
314                 if (getIntGroup(int_id) != Gicv3::G1NS) {
343         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
344              i = i + 2, int_id++) {
346             if (nsAccessToSecInt(int_id, is_secure_access))
351             if (irqConfig[int_id] == Gicv3::INT_EDGE_TRIGGERED) {
375                 for (int i = 0, int_id = first_intid;
376                      i < 8 * size && int_id < itLines; i++, int_id++) {
377                     val |= irqGrpmod[int_id] << i;
398         for (int i = 0, int_id = first_intid;
399              i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
400             val |= irqNsacr[int_id] << i;
416         int int_id = (addr - GICD_IROUTER.start()) / 8;
418         if (isNotSPI(int_id)) {
422         if (nsAccessToSecInt(int_id, is_secure_access))
424             if (irqNsacr[int_id] < 3) {
431                 return irqAffinityRouting[int_id] >> 32;
433                 return irqAffinityRouting[int_id] & 0xFFFFFFFF;
436             return irqAffinityRouting[int_id];
522         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
523              i++, int_id++) {
524             irqGroup[int_id] = data & (1 << i) ? 1 : 0;
525             DPRINTF(GIC, "Gicv3Distributor::write(): int_id %d group %d\n",
526                     int_id, irqGroup[int_id]);
538         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
539              i++, int_id++) {
541             if (nsAccessToSecInt(int_id, is_secure_access))
549                 if (!irqEnabled[int_id]) {
551                             "int_id %d enabled\n", int_id);
554                 irqEnabled[int_id] = true;
567         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
568              i++, int_id++) {
570             if (nsAccessToSecInt(int_id, is_secure_access))
578                 if (irqEnabled[int_id]) {
580                             "int_id %d disabled\n", int_id);
583                 irqEnabled[int_id] = false;
596         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
597              i++, int_id++) {
599             if (nsAccessToSecInt(int_id, is_secure_access))
601                 if (irqNsacr[int_id] == 0) {
611                         "int_id %d (SPI) pending bit set\n", int_id);
612                 irqPending[int_id] = true;
626         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
627              i++, int_id++) {
629             if (nsAccessToSecInt(int_id, is_secure_access))
631                 if (irqNsacr[int_id] < 2) {
640                 irqPending[int_id] = false;
641                 clearIrqCpuInterface(int_id);
655         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
656              i++, int_id++) {
658             if (nsAccessToSecInt(int_id, is_secure_access))
666                 irqActive[int_id] = 1;
679         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
680              i++, int_id++) {
682             if (nsAccessToSecInt(int_id, is_secure_access))
690                 if (irqActive[int_id]) {
692                             "int_id %d active cleared\n", int_id);
695                 irqActive[int_id] = false;
708         for (int i = 0, int_id = first_intid; i < size && int_id < itLines;
709                 i++, int_id++) {
713                 if (getIntGroup(int_id) != Gicv3::G1NS) {
721             irqPriority[int_id] = prio;
722             DPRINTF(GIC, "Gicv3Distributor::write(): int_id %d priority %d\n",
723                     int_id, irqPriority[int_id]);
746         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
747              i = i + 2, int_id++) {
748             irqConfig[int_id] = data & (0x2 << i) ?
751             DPRINTF(GIC, "Gicv3Distributor::write(): int_id %d config %d\n",
752                     int_id, irqConfig[int_id]);
771                 for (int i = 0, int_id = first_intid;
772                      i < 8 * size && int_id < itLines; i++, int_id++) {
773                     irqGrpmod[int_id] = bits(data, i);
793         for (int i = 0, int_id = first_intid;
794              i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
795             irqNsacr[int_id] = (data >> (2 * int_id)) & 0x3;
801         int int_id = (addr - GICD_IROUTER.start()) / 8;
803         if (isNotSPI(int_id)) {
807         if (nsAccessToSecInt(int_id, is_secure_access))
809             if (irqNsacr[int_id] < 3) {
817                 irqAffinityRouting[int_id] =
818                     (irqAffinityRouting[int_id] & 0xffffffff) | (data << 32);
820                 irqAffinityRouting[int_id] =
821                     (irqAffinityRouting[int_id] & 0xffffffff00000000) |
825             irqAffinityRouting[int_id] = data;
829                 "int_id %d GICD_IROUTER %#llx\n",
830                 int_id, irqAffinityRouting[int_id]);
995 Gicv3Distributor::sendInt(uint32_t int_id)
997     panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
998     panic_if(int_id > itLines, "Invalid SPI!");
999     irqPending[int_id] = true;
1001             "int_id %d (SPI) pending bit set\n", int_id);
1006 Gicv3Distributor::deassertSPI(uint32_t int_id)
1008     panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
1009     panic_if(int_id > itLines, "Invalid SPI!");
1010     irqPending[int_id] = false;
1011     clearIrqCpuInterface(int_id);
1017 Gicv3Distributor::route(uint32_t int_id)
1019     IROUTER affinity_routing = irqAffinityRouting[int_id];
1022     const Gicv3::GroupId int_group = getIntGroup(int_id);
1054 Gicv3Distributor::clearIrqCpuInterface(uint32_t int_id)
1056     auto cpu_interface = route(int_id);
1058         cpu_interface->resetHppi(int_id);
1065     for (int int_id = Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id < itLines;
1066          int_id++) {
1067         Gicv3::GroupId int_group = getIntGroup(int_id);
1070         if (irqPending[int_id] && irqEnabled[int_id] &&
1071             !irqActive[int_id] && group_enabled) {
1074             Gicv3CPUInterface *target_cpu_interface = route(int_id);
1079             if ((irqPriority[int_id] < target_cpu_interface->hppi.prio) ||
1080                 (irqPriority[int_id] == target_cpu_interface->hppi.prio &&
1081                 int_id < target_cpu_interface->hppi.intid)) {
1083                 target_cpu_interface->hppi.intid = int_id;
1084                 target_cpu_interface->hppi.prio = irqPriority[int_id];
1097 Gicv3Distributor::intStatus(uint32_t int_id) const
1099     panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
1100     panic_if(int_id > itLines, "Invalid SPI!");
1102     if (irqPending[int_id]) {
1103         if (irqActive[int_id]) {
1108     } else if (irqActive[int_id]) {
1116 Gicv3Distributor::getIntGroup(int int_id) const
1118     panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
1119     panic_if(int_id > itLines, "Invalid SPI!");
1122         if (irqGroup[int_id] == 1) {
1128         if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 0) {
1130         } else if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 1) {
1132         } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 0) {
1134         } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 1) {
1143 Gicv3Distributor::activateIRQ(uint32_t int_id)
1145     irqPending[int_id] = false;
1146     irqActive[int_id] = true;
1150 Gicv3Distributor::deactivateIRQ(uint32_t int_id)
1152     irqActive[int_id] = false;