dev/arm/gic_v3_cpu_interface.cc

1727     RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1729     if (apr) {
1730         apr &= apr - 1;
1731         isa->setMiscRegNoEffect(apr_misc_reg, apr);
1834     RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1835     apr |= (1 << reg_bit);
1836     isa->setMiscRegNoEffect(apr_idx, apr);
1870     RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1871     apr |= (1 << reg_bit);
1872     isa->setMiscRegNoEffect(apr_idx, apr);
2285     uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2289     if (apr) {
2290         return ctz32(apr) << (GIC_MIN_BPR + 1);