dev/arm/gic_v3_cpu_interface.cc

121       // Active Priorities Group 1 Registers
144       // Active Priorities Group 0 Registers
167       // Interrupt Group 0 Enable register EL1
184       // Interrupt Group 1 Enable register EL1
202       // Interrupt Group 1 Enable register EL3
272                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
302                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
422               if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
478               if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
624       // Hyp Active Priorities Group 0 Registers
641       // Hyp Active Priorities Group 1 Registers
743       // Active Priorities Group 1 Registers
766       // Active Priorities Group 0 Registers
843                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
922                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
1323       // Interrupt Group 0 Enable Register EL1
1335       // Virtual Interrupt Group 0 Enable register
1346       // Interrupt Group 1 Enable register EL1
1358       // Virtual Interrupt Group 1 Enable register
1369       // Interrupt Group 1 Enable register
1382       // Software Generated Interrupt Group 0 Register
1388       // Software Generated Interrupt Group 1 Register
1397       // Alias Software Generated Interrupt Group 1 Register
1459         ich_lrc.Group = requested_ich_lrc.Group;
1504           ich_lr_el2.Group = requested_ich_lr_el2.Group;
1570       // Hyp Active Priorities Group 0 Registers
1587       // Hyp Active Priorities Group 1 Registers
1701         // Group 1 non-secure interrupts not visible in Secure EL1
1863     Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
2072             if (ich_lr_el2.Group) {
2127         if (ich_lr_el2.Group) {
2176     Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2503     // vPE Group 0 Enabled. [bit 4]
2510     // vPE Group 0 Disabled. [bit 5]
2517     // vPE Group 1 Enabled. [bit 6]
2524     // vPE Group 1 Disabled. [bit 7]