dev/arm/gic_v3_cpu_interface.cc

116     RegVal value = isa->readMiscRegNoEffect(misc_reg);
180           value = ich_vmcr_el2.VENG0;
191           value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
198           value = ich_vmcr_el2.VENG1;
212           value = igrp_el3;
231                   // If the current priority mask value is in the range of
232                   // 0x00-0x7F a read access returns the value 0x0
235                   // If the current priority mask value is in the range of
237                   // the current value
242           value = rprio;
248           value = virtualHighestActivePriority();
259           value = getHPPIR0();
265           value = Gicv3::INTID_SPURIOUS;
275                   value = ich_lr_el2.vINTID;
289           value = getHPPIR1();
295           value = Gicv3::INTID_SPURIOUS;
305                   value = ich_lr_el2.vINTID;
319         value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
326         value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS);
335         value = ich_vmcr_el2.VBPR0;
346             value = ich_vmcr_el2.VBPR0 + 1;
347             value = value < 7 ? value : 7;
349             value = ich_vmcr_el2.VBPR1;
366             if ((value & 0x80) == 0) {
367                 // If the current priority mask value is in the range of
368                 // 0x00-0x7F a read access returns the value 0x00.
369                 value = 0;
370             } else if (value != 0xff) {
371                 // If the current priority mask value is in the range of
373                 // current value.
374                 value = (value << 1) & 0xff;
384           value = ich_vmcr_el2.VPMR;
409           value = int_id;
439           value = int_id;
465           value = int_id;
495           value = int_id;
512           value = icc_sre_el1;
531         value = icc_sre_el2;
552         value = icc_sre_el3;
563           value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
564           // Enforce value for RO bits
572           ICC_CTLR_EL1 icc_ctlr_el1 = value;
579           value = icc_ctlr_el1;
585           ICV_CTLR_EL1 icv_ctlr_el1 = value;
591           value = icv_ctlr_el1;
598           // Enforce value for RO bits
607           ICC_CTLR_EL3 icc_ctlr_el3 = value;
615           value = icc_ctlr_el3;
661         value = maintenanceInterruptStatus();
667         ICH_VTR_EL2 ich_vtr_el2 = value;
675         value = ich_vtr_el2;
682         value = eoiMaintenanceInterruptStatus();
688         value = 0;
696                 value |= (1 << lr_idx);
705         value = value >> 32;
711         value = value & 0xffffffff;
728     DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
729             miscRegName[misc_reg], value);
730     return value;
737     DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
1296                   // If the current priority mask value is in the range of
1301               // If the current priority mask value is in the range of
1303               // based on the Non-secure read of the priority mask value
1475         // valid value for the implemented INTID size. Any unused higher
1520           // valid value for the implemented INTID size. Any unused higher
1914  * Returns the priority group field for the current BPR value for the group.
2431     uint64_t value = 0;
2439             value |= (1 << lr_idx);
2443     return value;