dev/arm/gic_v3_cpu_interface.cc

269               ICH_LR_EL2 ich_lr_el2 =
272                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
275                   value = ich_lr_el2.vINTID;
299               ICH_LR_EL2 ich_lr_el2 =
302                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
305                   value = ich_lr_el2.vINTID;
419               ICH_LR_EL2 ich_lr_el2 =
422               if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
423                   int_id = ich_lr_el2.vINTID;
432                       ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
434                                               ich_lr_el2);
475               ICH_LR_EL2 ich_lr_el2 =
478               if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
479                   int_id = ich_lr_el2.vINTID;
488                       ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
490                                               ich_lr_el2);
691             ICH_LR_EL2 ich_lr_el2 =
694             if ((ich_lr_el2.State  == ICH_LR_EL2_STATE_INVALID) &&
695                 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
840               ICH_LR_EL2 ich_lr_el2 =
843                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
844               uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
919               ICH_LR_EL2 ich_lr_el2 =
922                   ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
923               uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
1500           ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1502           ich_lr_el2.State = requested_ich_lr_el2.State;
1503           ich_lr_el2.HW = requested_ich_lr_el2.HW;
1504           ich_lr_el2.Group = requested_ich_lr_el2.Group;
1510           ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1511                                 (ich_lr_el2.Priority & 0x07);
1523               ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1525               ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1532           ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1534           val = ich_lr_el2;
1634         ICH_LR_EL2 ich_lr_el2 =
1637         if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1638              (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1639             (ich_lr_el2.vINTID == int_id)) {
1895     ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1898     if (ich_lr_el2.HW) {
1900         if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1901             Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1902                 distributor->getIntGroup(ich_lr_el2.pINTID) :
1903                 redistributor->getIntGroup(ich_lr_el2.pINTID);
1904             deactivateIRQ(ich_lr_el2.pINTID, group);
1909     ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1910     isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
2068         ICH_LR_EL2 ich_lr_el2 =
2072             if (ich_lr_el2.Group) {
2120         ICH_LR_EL2 ich_lr_el2 =
2123         if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2127         if (ich_lr_el2.Group) {
2139         uint8_t prio = ich_lr_el2.Priority;
2159     ICH_LR_EL2 ich_lr_el2 =
2161     uint8_t prio = ich_lr_el2.Priority;
2176     Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2434         ICH_LR_EL2 ich_lr_el2 =
2437         if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2438             !ich_lr_el2.HW && ich_lr_el2.EOI) {
2473         ICH_LR_EL2 ich_lr_el2 =
2476         if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2480         if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {