dev/arm/gic_v2.cc

142     const Addr daddr = pkt->getAddr() - distRange.start();
145     DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
147     const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());
169 GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
171     if (GICD_IGROUPR.contains(daddr)) {
172         uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2;
177     if (GICD_ISENABLER.contains(daddr)) {
178         uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
183     if (GICD_ICENABLER.contains(daddr)) {
184         uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
189     if (GICD_ISPENDR.contains(daddr)) {
190         uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
195     if (GICD_ICPENDR.contains(daddr)) {
196         uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
201     if (GICD_ISACTIVER.contains(daddr)) {
202         uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
207     if (GICD_ICACTIVER.contains(daddr)) {
208         uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
213     if (GICD_IPRIORITYR.contains(daddr)) {
214         Addr int_num = daddr - GICD_IPRIORITYR.start();
236     if (GICD_ITARGETSR.contains(daddr)) {
237         Addr int_num = daddr - GICD_ITARGETSR.start();
254     if (GICD_ICFGR.contains(daddr)) {
255         uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
262     switch(daddr) {
285         panic("Tried to read Gic distributor at offset %#x\n", daddr);
293     const Addr daddr = pkt->getAddr() - cpuRange.start();
299     DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
302     pkt->setLE<uint32_t>(readCpu(ctx, daddr));
309 GicV2::readCpu(ContextID ctx, Addr daddr)
311     switch(daddr) {
383         panic("Tried to read Gic cpu at offset %#x\n", daddr);
391     const Addr daddr = pkt->getAddr() - distRange.start();
415             daddr, data_sz, pkt_data);
417     writeDistributor(ctx, daddr, pkt_data, data_sz);
424 GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
427     if (GICD_IGROUPR.contains(daddr)) {
428         uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2;
434     if (GICD_ISENABLER.contains(daddr)) {
435         uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
441     if (GICD_ICENABLER.contains(daddr)) {
442         uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
448     if (GICD_ISPENDR.contains(daddr)) {
449         uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
457     if (GICD_ICPENDR.contains(daddr)) {
458         uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
466     if (GICD_ISACTIVER.contains(daddr)) {
467         uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
472     if (GICD_ICACTIVER.contains(daddr)) {
473         uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
478     if (GICD_IPRIORITYR.contains(daddr)) {
479         Addr int_num = daddr - GICD_IPRIORITYR.start();
506     if (GICD_ITARGETSR.contains(daddr)) {
507         Addr int_num = daddr - GICD_ITARGETSR.start();
526     if (GICD_ICFGR.contains(daddr)) {
527         uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
535     switch(daddr) {
552         panic("Tried to write Gic distributor at offset %#x\n", daddr);
560     const Addr daddr = pkt->getAddr() - cpuRange.start();
567             ctx, daddr, data);
569     writeCpu(ctx, daddr, data);
576 GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
578     switch(daddr) {
626         warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
629         warn("GIC DIR write ignored because not implemented: %#x\n", daddr);
632         panic("Tried to write Gic cpu at offset %#x\n", daddr);