Lines Matching defs:addr

571     const Addr addr(pkt->getAddr());
575 if (ctrlRange.contains(addr)) {
576 value = ctrlRead(addr - ctrlRange.start(), size);
577 } else if (timerRange.contains(addr)) {
578 value = timerRead(addr - timerRange.start(), size);
580 panic("Invalid address: 0x%x\n", addr);
583 DPRINTF(Timer, "Read 0x%x <- 0x%x(%i)\n", value, addr, size);
603 const Addr addr(pkt->getAddr());
607 DPRINTF(Timer, "Write 0x%x -> 0x%x(%i)\n", value, addr, size);
608 if (ctrlRange.contains(addr)) {
609 ctrlWrite(addr - ctrlRange.start(), size, value);
610 } else if (timerRange.contains(addr)) {
611 timerWrite(addr - timerRange.start(), size, value);
613 panic("Invalid address: 0x%x\n", addr);
621 GenericTimerMem::ctrlRead(Addr addr, size_t size) const
624 switch (addr) {
633 warn("Reading from unimplemented control register (0x%x)\n", addr);
643 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
647 switch (addr) {
652 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
661 GenericTimerMem::ctrlWrite(Addr addr, size_t size, uint64_t value)
664 switch (addr) {
669 warn("Write to unimplemented control register (0x%x)\n", addr);
684 addr, size);
688 switch (addr) {
695 addr, size);
704 GenericTimerMem::timerRead(Addr addr, size_t size) const
707 switch (addr) {
724 warn("Read from unimplemented timer register (0x%x)\n", addr);
758 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
762 switch (addr) {
779 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
788 GenericTimerMem::timerWrite(Addr addr, size_t size, uint64_t value)
791 switch (addr) {
793 warn("Unimplemented timer register (0x%x)\n", addr);
833 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
837 switch (addr) {
845 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);