Lines Matching refs:self
129 def generateDeviceTree(self, state):
136 if int(self.conf_device_bits) == 8:
138 elif int(self.conf_device_bits) == 12:
151 state.addrCells(self.conf_base) +
152 state.sizeCells(self.conf_size) ))
161 ranges += self.pciFdtAddr(space=1, addr=0)
162 ranges += state.addrCells(self.pci_pio_base)
166 ranges += self.pciFdtAddr(space=2, addr=0)
171 if str(self.int_policy) == 'ARM_PCI_INT_DEV':
172 gic = self._parent.unproxy(self).gic
183 for i in range(int(self.int_count)):
185 int(self.int_base) - 32 + i, 1)
187 interrupts += self.pciFdtAddr(device=i, addr=0) + \
193 int_count = int(self.int_count)
197 intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0]
203 if self._dma_coherent:
215 def generateDeviceTree(self, state):
216 node = FdtNode("sysreg@%x" % long(self.pio_addr))
219 state.addrCells(self.pio_addr) +
223 node.appendPhandle(self)
249 def generateDeviceTree(self, state):
250 phandle = state.phandle(self)
254 [0x1, int(self.device)]))
256 freq = int(1.0/self.freq.value) # Values are stored as a clock period
260 node.appendPhandle(self)
301 def generateDeviceTree(self, state):
306 for obj in self._children.values():
310 io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self))
334 def generateDeviceTree(self, state):
338 for obj in self._children.values():
342 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self))
361 def generateDeviceTree(self, state):
362 node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
363 0x1000, [int(self.int_num)])
368 realview = self._parent.unproxy(self)
406 def generateDeviceTree(self, state):
413 1, int(self.int_phys_s.num) - 16, 0xf08,
414 1, int(self.int_phys_ns.num) - 16, 0xf08,
415 1, int(self.int_virt.num) - 16, 0xf08,
416 1, int(self.int_hyp.num) - 16, 0xf08,
418 clock = state.phandle(self.clk_domain.unproxy(self))
438 def generateDeviceTree(self, state):
439 node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
440 0x1000, [int(self.int_num)])
443 clock = state.phandle(self.clk_domain.unproxy(self))
455 def generateDeviceTree(self, state):
456 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
457 0x1000, [int(self.int_num)])
460 clock = state.phandle(self.clk_domain.unproxy(self))
498 def endpointPhandle(self):
501 def generateDeviceTree(self, state):
503 endpoint_node.appendPhandle(self.endpointPhandle())
505 for encoder_node in self.encoder.generateDeviceTree(state):
506 encoder_endpoint = self.encoder.endpointNode()
510 [ state.phandle(self.encoder.endpointPhandle()) ]))
512 [ state.phandle(self.endpointPhandle()) ]))
520 node = self.generateBasicPioDeviceNode(state, 'hdlcd',
521 self.pio_addr, 0x1000, [63])
524 node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk)))
531 node.append(FdtPropertyStrings("status", [ self._status ]))
533 self.addIommuProperty(state, node)
545 def _on_chip_devices(self):
548 def _off_chip_devices(self):
553 def _attach_device(self, device, bus, dma_ports=None):
562 def _attach_io(self, devices, *args, **kwargs):
564 self._attach_device(d, *args, **kwargs)
566 def _attach_clk(self, devices, clkdomain):
571 def attachPciDevices(self):
574 def enableMSIX(self):
577 def onChipIOClkDomain(self, clkdomain):
578 self._attach_clk(self._on_chip_devices(), clkdomain)
580 def offChipIOClkDomain(self, clkdomain):
581 self._attach_clk(self._off_chip_devices(), clkdomain)
583 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
584 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
586 bridge.ranges = self._off_chip_ranges
588 def attachIO(self, *args, **kwargs):
589 self._attach_io(self._off_chip_devices(), *args, **kwargs)
591 def setupBootLoader(self, mem_bus, cur_sys, loc):
601 def generateDeviceTree(self, state):
604 state.phandle(self.gic)))
606 for subnode in self.recurseDeviceTree(state):
611 def annotateCpuDeviceNode(self, cpu, state):
668 def attachOnChipIO(self, bus, bridge):
669 self.gic.pio = bus.master
670 self.l2x0_fake.pio = bus.master
671 self.a9scu.pio = bus.master
672 self.global_timer.pio = bus.master
673 self.local_cpu_timer.pio = bus.master
676 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
677 self.a9scu.pio_addr - 1),
678 AddrRange(self.flash_fake.pio_addr,
679 self.flash_fake.pio_addr + \
680 self.flash_fake.pio_size - 1)]
684 def onChipIOClkDomain(self, clkdomain):
685 self.gic.clk_domain = clkdomain
686 self.l2x0_fake.clk_domain = clkdomain
687 self.a9scu.clkdomain = clkdomain
688 self.local_cpu_timer.clk_domain = clkdomain
693 def attachIO(self, bus):
694 self.uart.pio = bus.master
695 self.realview_io.pio = bus.master
696 self.pci_host.pio = bus.master
697 self.timer0.pio = bus.master
698 self.timer1.pio = bus.master
699 self.clcd.pio = bus.master
700 self.clcd.dma = bus.slave
701 self.kmi0.pio = bus.master
702 self.kmi1.pio = bus.master
703 self.cf_ctrl.pio = bus.master
704 self.cf_ctrl.dma = bus.slave
705 self.dmac_fake.pio = bus.master
706 self.uart1_fake.pio = bus.master
707 self.uart2_fake.pio = bus.master
708 self.uart3_fake.pio = bus.master
709 self.smc_fake.pio = bus.master
710 self.sp810_fake.pio = bus.master
711 self.watchdog_fake.pio = bus.master
712 self.gpio0_fake.pio = bus.master
713 self.gpio1_fake.pio = bus.master
714 self.gpio2_fake.pio = bus.master
715 self.ssp_fake.pio = bus.master
716 self.sci_fake.pio = bus.master
717 self.aaci_fake.pio = bus.master
718 self.mmc_fake.pio = bus.master
719 self.rtc.pio = bus.master
720 self.flash_fake.pio = bus.master
721 self.energy_ctrl.pio = bus.master
725 def offChipIOClkDomain(self, clkdomain):
726 self.uart.clk_domain = clkdomain
727 self.realview_io.clk_domain = clkdomain
728 self.timer0.clk_domain = clkdomain
729 self.timer1.clk_domain = clkdomain
730 self.clcd.clk_domain = clkdomain
731 self.kmi0.clk_domain = clkdomain
732 self.kmi1.clk_domain = clkdomain
733 self.cf_ctrl.clk_domain = clkdomain
734 self.dmac_fake.clk_domain = clkdomain
735 self.uart1_fake.clk_domain = clkdomain
736 self.uart2_fake.clk_domain = clkdomain
737 self.uart3_fake.clk_domain = clkdomain
738 self.smc_fake.clk_domain = clkdomain
739 self.sp810_fake.clk_domain = clkdomain
740 self.watchdog_fake.clk_domain = clkdomain
741 self.gpio0_fake.clk_domain = clkdomain
742 self.gpio1_fake.clk_domain = clkdomain
743 self.gpio2_fake.clk_domain = clkdomain
744 self.ssp_fake.clk_domain = clkdomain
745 self.sci_fake.clk_domain = clkdomain
746 self.aaci_fake.clk_domain = clkdomain
747 self.mmc_fake.clk_domain = clkdomain
748 self.rtc.clk_domain = clkdomain
749 self.flash_fake.clk_domain = clkdomain
750 self.energy_ctrl.clk_domain = clkdomain
782 def _on_chip_devices(self):
784 self.gic, self.vgic,
785 self.local_cpu_timer
787 if hasattr(self, "gicv2m"):
788 devices.append(self.gicv2m)
789 devices.append(self.hdlcd)
830 def _off_chip_devices(self):
832 self.uart,
833 self.realview_io,
834 self.pci_host,
835 self.timer0,
836 self.timer1,
837 self.clcd,
838 self.kmi0,
839 self.kmi1,
840 self.cf_ctrl,
841 self.rtc,
842 self.vram,
843 self.l2x0_fake,
844 self.uart1_fake,
845 self.uart2_fake,
846 self.uart3_fake,
847 self.sp810_fake,
848 self.watchdog_fake,
849 self.aaci_fake,
850 self.lan_fake,
851 self.usb_fake,
852 self.mmc_fake,
853 self.energy_ctrl,
856 if hasattr(self, "ide"):
857 devices.append(self.ide)
858 if hasattr(self, "ethernet"):
859 devices.append(self.ethernet)
863 def attachPciDevices(self):
864 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
866 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
869 def enableMSIX(self):
870 self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000,
872 self.gicv2m = Gicv2m()
873 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
875 def setupBootLoader(self, mem_bus, cur_sys, loc):
894 def setupBootLoader(self, mem_bus, cur_sys, loc):
1023 def _on_chip_devices(self):
1025 self.generic_timer,
1056 def _off_chip_devices(self):
1058 self.realview_io,
1059 self.uart[0],
1060 self.kmi0,
1061 self.kmi1,
1062 self.rtc,
1063 self.pci_host,
1064 self.energy_ctrl,
1065 self.clock24MHz,
1066 self.vio[0],
1067 self.vio[1],
1070 def attachPciDevice(self, device, *args, **kwargs):
1071 device.host = self.pci_host
1072 self._attach_device(device, *args, **kwargs)
1074 def setupBootLoader(self, mem_bus, cur_sys, loc):
1089 def generateDeviceTree(self, state):
1091 dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
1112 def _on_chip_devices(self):
1113 return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
1114 self.gic, self.vgic, self.gicv2m,
1121 def _on_chip_devices(self):
1122 return super(VExpress_GEM5_V1,self)._on_chip_devices() + [
1123 self.hdlcd,
1134 def _on_chip_devices(self):
1135 return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
1136 self.gic, self.gic.its
1139 def setupBootLoader(self, mem_bus, cur_sys, loc):
1141 super(VExpress_GEM5_V2_Base,self).setupBootLoader(mem_bus,
1148 def _on_chip_devices(self):
1149 return super(VExpress_GEM5_V2,self)._on_chip_devices() + [
1150 self.hdlcd,