Lines Matching defs:port
72 * defined. It has two port subclasses inherited from MasterPort for
197 * When instruction cache port receives a retry, schedule event
203 * When data cache port receives a retry, schedule event
209 * When data cache port receives a response, this calls the dcache
340 * port sends packet succesfully, determine the tick to send the next
433 port(_port),
464 * arguments. Calls the port's sendTimingReq() and returns true if
507 /** Reference of the port to be used to issue memory requests. */
508 MasterPort& port;
553 * port sends packet succesfully, the generator checks which instructions
860 port(_port),
934 * parameters. Calls the port's sendTimingReq() and returns a packet
958 * release the dependents on it. This is called from the dcache port
993 /** Reference of the port to be used to issue memory requests. */
994 MasterPort& port;
1148 /** Used to get a reference to the icache port. */
1151 /** Used to get a reference to the dcache port. */